Patents by Inventor Mark Fang

Mark Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tracking and Manipulating Cellular RNA via Nuclear Delivery of CRISPR/CAS9
    Publication number: 20230365951
    Abstract: Cas9 polypeptides which target RNA and methods of using them are provided.
    Type: Application
    Filed: April 25, 2023
    Publication date: November 16, 2023
    Inventors: Eugene Yeo, David A. Nelles, Mark Fang, Ranjan Batra
  • Tracking and manipulating cellular RNA via nuclear delivery of CRISPR/CAS9
    Patent number: 11667903
    Abstract: Cas9 polypeptides which target RNA and method of using them are provided.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 6, 2023
    Assignee: The Regents of the University of California
    Inventors: Eugene Yeo, David A. Nelles, Mark Fang, Ranjan Batra
  • Tracking and Manipulating Cellular RNA via Nuclear Delivery of CRISPR/CAS9
    Publication number: 20200239863
    Abstract: Cas9 polypeptides which target RNA and methods of using them are provided
    Type: Application
    Filed: February 19, 2020
    Publication date: July 30, 2020
    Inventors: Eugene Yeo, David A. Nelles, Mark Fang, Ranjan Batra
  • TRACKING AND MANIPULATING CELLULAR RNA VIA NUCLEAR DELIVERY OF CRISPR/CAS9
    Publication number: 20190040370
    Abstract: Cas9 polypeptides which target RNA and methods of using them are provided.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 7, 2019
    Inventors: Gene Yeo, David A. Nelles, Mark Fang, Ranjan Batra
  • TRACKING AND MANIPULATING CELLULAR RNA VIA NUCLEAR DELIVERY OF CRISPR/CAS9
    Publication number: 20170145394
    Abstract: Cas9 polypeptides which target RNA and methods of using them are provided.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 25, 2017
    Inventors: Gene Yeo, David A. Nelles, Mark Fang, Ranjan Batra
  • Multi-resource aware partitioning for integrated circuits
    Patent number: 8473881
    Abstract: A method of partitioning a circuit design can include identifying a circuit design in which components of the circuit design are assigned to each of a plurality of regions, wherein each region corresponds to a physical portion of an integrated circuit. A maximum oversubscription region can be determined for a selected component type from the plurality of regions. A target region from the plurality of regions can be selected that is adjacent to the region of maximum oversubscription. The method also can include re-assigning, by a processor, a selected number of components of the maximum oversubscription region to the target region.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: June 25, 2013
    Assignee: Xilinx, Inc.
    Inventors: Wei Mark Fang, Vishal Suthar, Srinivasan Dasasathyan
  • Control set constraint driven force directed analytical placer for programmable integrated circuits
    Patent number: 8230377
    Abstract: A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Wei Mark Fang, Srinivasan Dasasathyan
  • Method of and system for placing clock circuits in an integrated circuit
    Patent number: 8225262
    Abstract: A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: July 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Marvin Tom, Wei Mark Fang, Srinivasan Dasasathyan