Abstract: A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.

Abstract: A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being <100>. In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.

Abstract: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

Abstract: A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being <100>. In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.