Abstract: An indication that a power supply is ramped up to a threshold level is received. A circuit is woken up in response to receiving the indication if a control field of configuration information is in a first state, and the circuit is not woken up in response to receiving the indication if the control field of configuration information is in a second state.

Abstract: A protection circuit is disclosed, for preventing access to stored security key data after the security key is no longer used. The protection circuit performs operations on a programming circuit used to program a bit of the security key. The protection circuit prevents inspection of the security key bit, using several techniques. Subsequent inspection of the programming circuit does not reveal the value of the security key bit.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data while the processor is in a standby mode and transfer data to the processor while the processor is executing instructions.

Abstract: A graphics system includes a single buffer coupled between a graphics controller and a display controller. The graphics controller rotates a frame generated by an application and writes the rotated frame into the buffer. The rotation is performed a segment (e.g., a quartile of a frame) at a time. Each time the display controller completes displaying a frame quartile, the display controller signals the graphics controller to rotate a corresponding quartile of a next frame. The reduction in buffer space reduces power consumption and improves performance of the system.

Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

Abstract: A memory device includes a flag register to modify the address map of the memory device based on the state of an input node on the memory device.

Abstract: A memory controller partitions memory into secure partitions and non-secure partitions.

Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Abstract: Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.

Abstract: A wireless device dynamically programs a control register for a command-chain driven DMA device. The control register stores a beginning address of the linked list of commands and a secure bit. The secure bit is set if the transaction writing register is secure and a bit in the data being written into the register is set. DMA devices and other bus-mastering peripherals perform tasks described via a command chain that has access to secure resources when the processor is operating in the secure mode and the secure bit is set.

Abstract: A technique includes sharing common external terminals of a memory device to communicate data and an address with the memory device for a given memory operation. Different sets of address bits indicative of the address are communicated over the common external terminals at different times.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data while the processor is in a standby mode and transfer data to the processor while the processor is executing instructions.

Abstract: In some embodiments a Universal Serial Bus On-The-Go (USB OTG) device includes a USB device controller, a USB host controller, a USB OTG transceiver, and a controller to control a coupling between the USB device controller, the USB host controller, and the USB OTG transceiver, and to control whether the USB device controller, the USB host controller, or a combination of the USB device controller and the USB host controller controls the USB OTG transceiver. Other embodiments are described and claimed.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: Circuits in a processor may provide an indication that power supplies are ready when waking from a reduced power state. The processor may include timers to measure a period of time, and may utilize voltage detectors to detect the voltages on the power supplies. A control register in the processor may influence the operation.

Abstract: A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.

Abstract: Trusted code may be patched in a manner that resists tampering from non-trusted sources. In some embodiments, the patches may be moved into a patch cache in a trusted processing module for execution.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to write data is provided. The apparatus may include a circuit to deassert a chip select signal to latch data in a first memory after asserting a write enable signal and prior to deasserting the write enable signal, wherein the chip select signal is coupled to the first memory and the write enable signal is coupled to both the first memory and a second memory. The method may include asserting a chip select signal after asserting of a write enable signal and then deasserting the chip select signal to latch the data in a memory, wherein the deasserting of the chip select signal occurs prior to the deasserting of the write enable signal. Other embodiments are described and claimed.

Abstract: Direct memory access control may utilize a direct memory access register adapted to hold a descriptor.

Abstract: An apparatus includes a processor to control a boot-up of an electronic device in response to a detection of tampering with the device. In some embodiments of the invention, the processor may detect tampering by authenticating a source of a boot image used during the boot-up; and the processor may detect tampering by verifying the integrity of the boot image. In some embodiments of the invention, the processor may control a transition of the electronic device from a first state to a second power state in response to a detection of tampering with the device. The electronic device consumes more power in the second power state than in the first power state.