Abstract: A method for tracking a pluggable component associated with an electronic device is provided. The method may include identifying at least one field of vital product data (VPD) information associated with the pluggable component. The method may also include decoding the at least one field of VPD information. Additionally, the method may include determining, based on the decoding of the at least one field, when a hardware id associated with the pluggable component is valid. The method may further include generating a pairing signature based on the hardware id being valid.

Abstract: A method, system, and computer program product to manage license key information in a system including a feature requiring the license key information are described. The method includes storing, automatically, a backup copy of the license key information from a primary copy of the license key information after installation of a feature requiring the license key information on the system. The method also includes recovering, automatically, the license key information whenever the license key information is required to be installed.

Abstract: A method, system, and computer program product to manage license key information in a system including a feature requiring the license key information are described. The method includes storing, automatically, a backup copy of the license key information from a primary copy of the license key information after installation of a feature requiring the license key information on the system. The method also includes recovering, automatically, the license key information whenever the license key information is required to be installed.

Abstract: Embodiments of the present invention provide an approach for protecting electronic devices against the use of unqualified and/or unauthorized (e.g., “grey market”) hardware components. Specifically, in a typical embodiment, a hardware component that a user is attempting to use with an electronic device will be detected. Then, the device information associated with the hardware component (e.g., serial number, vital product data (VPD), etc.) will be identified from the hardware component (e.g., as stored therein).

Abstract: Embodiments of the present invention provide an approach for protecting electronic devices against the use of unqualified and/or unauthorized (e.g., “grey market”) hardware components. Specifically, in a typical embodiment, a hardware component that a user is attempting to use with an electronic device will be detected. Then, the device information associated with the hardware component (e.g., serial number, vital product data (VPD), etc.) will be identified from the hardware component (e.g., as stored therein).

Abstract: A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.

Abstract: A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.

Abstract: A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

Abstract: A computer system having: a central processing unit (CPU), having a system bus associated therewith, a first bus interface circuit (BIC) in circuit communication with the CPU and generating a peripheral bus, such as the MICRO CHANNEL bus, a floppy drive controller (FDC), and an Integrated Drive Electronics (IDE) hardfile (hard drive). The IDE hardfile is in electrical circuit communication with the peripheral bus via a second bus interface circuit. The second bus interface circuit includes a writable latch having at least two states and in circuit communication with the peripheral bus. The latch states are selectable by the CPU via the system bus. The second bus interface circuit also has an access control circuit in circuit communication with the peripheral bus, the system bus, and the latch for selectively allowing data transfers between the CPU and either the FDC or the IDE hard drive, depending on the state of the latch.

Abstract: A personal computer has two possible memory sizes differing by the maximum number SIMMs that can be installed. Each SIMM stores presence detect bits indicating the size and speed of the SIMM. An I/O controller includes a memory detect port which is used to read the presence detect bits from the SIMMs. The controller further includes a logic circuit that is set in accordance with the memory size to selectively control driving the presence detect bits or empty socket bits onto a data bus.