Abstract: In exemplary embodiments, a waveform processor system may update pixel state information as a function of current pixel state information (e.g., intensity, color) by comparing a randomized value to a set of predetermined threshold values that correspond to different permitted pixel states. In an illustrative example, each time a display screen is updated, the image may represent multiple (e.g., 2000) triggered sweeps of the waveform. For each triggered sweep, the waveform data is associated with specific pixels on the display screen. To determine how to update each pixel's state (e.g., brightness, color) for the next screen update, each waveform hit on a pixel may initiate a comparison between a randomized value (e.g., pseudorandom number) and the predetermined threshold value for the pixel's current pixel state. In some examples, the pixel state may be increased to the next level if the randomized value exceeds the predetermined threshold value.

Abstract: In exemplary embodiments, a waveform processor system may update pixel state information as a function of current pixel state information (e.g., intensity, color) by comparing a randomized value to a set of predetermined threshold values that correspond to different permitted pixel states. In an illustrative example, each time a display screen is updated, the image may represent multiple (e.g., 2000) triggered sweeps of the waveform. For each triggered sweep, the waveform data is associated with specific pixels on the display screen. To determine how to update each pixel's state (e.g., brightness, color) for the next screen update, each waveform hit on a pixel may initiate a comparison between a randomized value (e.g., pseudorandom number) and the predetermined threshold value for the pixel's current pixel state. In some examples, the pixel state may be increased to the next level if the randomized value exceeds the predetermined threshold value.

Abstract: A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.