Abstract: An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.

Abstract: An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.

Abstract: An integrated circuit (IC) with negative potential protection includes a switch, a gate drive circuit and a comparator. The switch includes a double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The switch also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket. An output of the gate drive circuit is coupled across a gate and a source of the switch. An output of the comparator is coupled to a second input of the gate drive circuit and a first input of the comparator receives a reference signal. A second input of the comparator is coupled to the epitaxial pocket. The comparator provides a turn-on signal that causes the switch to conduct current, when a signal at the second input of the comparator is below the reference signal.

Abstract: An integrated driver with improved load current sense capability includes a first transistor, a first amplifier, a second transistor, a third transistor, a second amplifier and a fourth transistor. The integrated driver allows for significantly better fault handling capability, provides accurate thermal and current sensing capability and reduces I/O pin count over prior designs.

Abstract: An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.

Abstract: A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diodes comprises a second-type well formed in the substrate, a second-type Zener region formed in the second-type well and a first-type+ region formed over the second-type Zener region between a first and second second-type+ region.

Abstract: A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.