Abstract: A telephone answering device for permitting a person to switch an incoming telephone call to a message recording or answering machine for taking or recording a message from a caller onto at least one cassette of the message recording or answering machine. This device includes a telephone instrument, at least one message recording or answering machine, and a person actuated switch. The person actuated switch has a first "normal" position to permit a person to receive calls using the telephone instrument and a second position for permitting a person to switch the caller to the message recording or answering machine after the person has initially spoken to the caller.

Abstract: A real time control system is disclosed for controlling the sequential execution of scheduled operatons such as in process control or broadcast scheduling applications. The system uses a fail safe feature characterized as a sender/listener architecture. An external clock input to the sender and the listener assures synchronous sequential stepping through identical schedules stored in each processor. Under normal operation, the sender processor controls the execution of events as they are sent from a host computer connected to the system, Unscheduled events or errors are processed by being added to the schedule in real time for both the sender and listener processors. The listener processor monitors the sender's signaling in the controlled network and, in the case of a failure in the sender, the listener immediately assumes control of the system as the new sender.

Abstract: A method for controlling a processor in a data processing system so that multiple events are serviced on a single interrupt level. On the occurrence of a first interrupt request the processor is forced to run the routine that services the interrupt in a background mode. This is accomplished by immediately clearing the interrupt source, thus permitting the processor to accept new interrupt requests on the same level. On the occurrence of a second interrupt request, at the same level, the processor branches from executing the first interrupt routine on the background mode to service the second interrupt request on an interrupt level or foreground mode.