Patents by Inventor Mark Hakey

Mark Hakey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060035460
    Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 16, 2006
    Inventors: Richard Wise, Bomy Chen, Mark Hakey, Hongwen Yan
  • Publication number: 20060022221
    Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Applicant: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell
  • Publication number: 20060011990
    Abstract: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).
    Type: Application
    Filed: July 15, 2004
    Publication date: January 19, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
  • Publication number: 20060008927
    Abstract: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.
    Type: Application
    Filed: September 7, 2005
    Publication date: January 12, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, David Horak, Charles Koburger, Mark Masters, Peter Mitchell
  • Publication number: 20050287764
    Abstract: The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.
    Type: Application
    Filed: August 19, 2005
    Publication date: December 29, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Doris, Mark Hakey, Akihisa Sekiguchi
  • Publication number: 20050286293
    Abstract: A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, David Horak, Charles Koburger, Mark Masters, Peter Mitchell
  • Publication number: 20050266627
    Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
    Type: Application
    Filed: July 13, 2005
    Publication date: December 1, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Peter Mitchell, Larry Nesbit
  • Publication number: 20050242378
    Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.
    Type: Application
    Filed: July 6, 2005
    Publication date: November 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Larry Nesbit
  • Publication number: 20050245008
    Abstract: A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Doris, Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
  • Publication number: 20050237501
    Abstract: An apparatus, system and method for use with a photolithographic system. In accordance with one embodiment, the photolithographic system of the present invention includes a workpiece support member for supporting a semiconductor wafer. A substantially transparent cover member is disposed over the workpiece support member to form a substantially enclosed workpiece cell therebetween. The enclosed workpiece cell is filled with a first immersion fluid having suitable refractive properties. The cover member, having suitable refractive properties, includes an upper surface contoured to form an open reservoir containing a second immersion fluid, having suitable refractive properties, and in which a final lens element may be immersed during a lithography process.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 27, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, David Horal, Charles Koburger, Peter Mitchell
  • Publication number: 20050239284
    Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 27, 2005
    Applicant: International Business Machines Corporation
    Inventors: Richard Wise, Bomy Chen, Mark Hakey, Hongwen Yan
  • Publication number: 20050213061
    Abstract: A photolithographic apparatus, system and method employing an improved refractive medium. The photolithographic apparatus may be used in an immersion lithography system for projecting light onto a workpiece such as a semiconductor wafer. In one embodiment, the photolithographic apparatus includes a container containing a transparent fluid. The fluid container is positioned between a lens element and the wafer. The container is further characterized as having a substantially flexible and transparent bottom membrane contacting an upper surface of the wafer and overlapping at least one side edge of the wafer such that a fluid filled skirt is formed extending beyond the edges of the wafer.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 29, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Hakey, David Horak, Charles Koburger, Peter Mitchell
  • Publication number: 20050202607
    Abstract: A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Hofak, Charles Koburger, Peter Mitchell, Larry Nesbit
  • Publication number: 20050202322
    Abstract: Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell, Larry Nesbit
  • Publication number: 20050189655
    Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Applicant: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark Hakey, David Horak, Charles Koburger, Mark Masters, Peter Mitchell, Stanislav Polonsky
  • Publication number: 20050179029
    Abstract: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 18, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell, Larry Nesbit
  • Publication number: 20050167655
    Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell, Larry Nesbit
  • Publication number: 20050167740
    Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Peter Mitchell, Larry Nesbit
  • Publication number: 20050158673
    Abstract: A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in the balloon also exhibits good optical properties, including a refractive index higher than that of air. Light from the lithography light source passes through a mask, through a top layer of the balloon membrane, through the contained liquid, through a bottom layer of the balloon membrane, and onto the workpiece where it alters portions of the photoresist. As the liquid has a low absorption and a higher refractive index than air, the liquid-filled balloon system enhances resolution. Thus, the balloon provides optical benefits of liquid immersion without the complications of maintaining a liquid between (and in contact with) a lithographic light source mechanism and workpiece.
    Type: Application
    Filed: January 21, 2004
    Publication date: July 21, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Hakey, David Horak, Charles Koburger, Peter Mitchell
  • Publication number: 20050145803
    Abstract: An apparatus for immersion optical lithography having a lens capable of relative movement in synchrony with a horizontal motion of a semiconductor wafer in a liquid environment where the synchronous motion of the lens apparatus and semiconductor wafer advantageously reduces the turbulence and air bubbles associated with a liquid environment. The relative motions of the lens and semiconductor wafer are substantially the same as the scanning process occurs resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption of the liquid environment.
    Type: Application
    Filed: December 31, 2003
    Publication date: July 7, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Hakey, David Horak, Charles Koburger, Peter Mitchell