Abstract: Method for producing a silicon ingot, comprising the following steps: providing a container to receive a silicon melt, providing a temperature control device to control the temperature of the silicon melt in the container, arranging raw material in the container comprising silicon and at least one nucleation agent to assist a heterogeneous nucleation in the silicon melt, and control of the temperature in the container for the directed solidification of the silicon melt, the nucleation agent comprising nanoscale particles.

Abstract: A device for the production of silicon blocks comprises a vessel for receiving a silicon melt, the vessel comprising a vessel wall comprising at least one side wall and a bottom as well as an inside and an outside and a central longitudinal axis, and means for creating a temperature field on the inside of the bottom, the temperature field having a temperature gradient at the bottom of the vessel which is perpendicular to the central longitudinal axis at least in some regions when the silicon melt cools down for crystallization.

Abstract: Method for producing a silicon ingot comprising the following steps: providing a container to receive a silicon melt, providing a temperature control device to control the temperature of the silicon melt in the container, arranging raw material in the container comprising silicon and at least one hydrogen-containing additive to reduce the formation of dislocations, and control of the temperature in the container (3) for the directed solidification of the silicon melt.

Abstract: Method for producing a silicon ingot, comprising the following steps: providing a container to receive a silicon melt, providing a temperature control device to control the temperature of the silicon melt in the container, arranging raw material in the container comprising silicon and at least one nucleation agent to assist a heterogeneous nucleation in the silicon melt, and control of the temperature in the container for the directed solidification of the silicon melt , the nucleation agent comprising nanoscale particles.

Abstract: A method for producing silicon blocks comprises providing a crucible for receiving a silicon melt, with a base and a plurality of side walls connected to the base, attaching nuclei at least on an inner side of the base of the crucible, the nuclei having a melt temperature, which is greater than the melt temperature of silicon, filling the crucible with the silicon melt, solidifying the silicon melt beginning on the nuclei and removing the solidified silicon from the crucible.

Abstract: A device for the production of silicon blocks comprises a vessel for receiving a silicon melt, the vessel comprising a vessel wall comprising at least one side wall and a bottom as well as an inside and an outside and a central longitudinal axis, and means for creating a temperature field on the inside of the bottom, the temperature field having a temperature gradient at the bottom of the vessel which is perpendicular to the central longitudinal axis at least in some regions when the silicon melt cools down for crystallization.

Abstract: A device for the production of silicon blocks comprising a vessel for receiving a silicon melt with at least one vessel wall, with the at least one vessel wall comprising a nucleation-inhibiting coating on at least part of an inside or with the at least one vessel wall consisting of a nucleation-inhibiting material.

Abstract: A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned in such a way that it is removed from the surface of the elevated region and from an edge region of the insulation layer, said edge region adjoining the sidewall of the elevated region. A material is implanted into the surface of the elevated region and also into the edge region of the insulation layer. The material preferably alters the properties of the surface of the elevated region and also increases the etching rate of the insulation layer. The mask layer is removed and the insulation layer is subjected to a whole-area etching step.

Abstract: A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned in such a way that it is removed from the surface of the elevated region and from an edge region of the insulation layer, said edge region adjoining the sidewall of the elevated region. A material is implanted into the surface of the elevated region and also into the edge region of the insulation layer. The material preferably alters the properties of the surface of the elevated region and also increases the etching rate of the insulation layer. The mask layer is removed and the insulation layer is subjected to a whole-area etching step.

Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA?; AA?;) are provided. said sub-structures (STI; AA; AA?; AA?,) having a first sub-structure (AA?) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA?). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.

Abstract: A process for abrasive machining of surfaces of semiconductor wafers, in particular during the production of electronic memory elements, is described. In the process, a topography of the surfaces of a plurality of wafers is planarized by an at least partially mechanical route. In a further process step which takes place at a later stage, further material is removed from the planarization surfaces by the action of a liquid, chemical composition (etchback). After the planarization step and before the etchback step, a layer thickness measurement of the planarized layer is carried. The method is distinguished by the fact that the measurement results of the layer thickness measurement are used as the basis for the automatic selection or formulation of one of a plurality of chemical compositions and/or the time of action of a selected or formulated chemical composition for carrying out the etchback step.

Abstract: Method for fabricating a trench isolation structure The invention provides a method for fabricating a trench isolation structure, comprising the following steps: forming a mask (3) on a substrate (1); forming at least one trench (2) in the substrate (1) by means of the mask (3); carrying out selective deposition of a first insulation material (5) to at least partially fill the at least one trench (2) in the substrate (1) with the insulation material (5) in the presence of the mask (3); and applying a second insulation material (6) over the entire surface of the structure in order to fill the at least one trench (2) in the substrate (1) at least up to the top side of the mask (3).

Abstract: A process is described for the chemical mechanical machining of semiconductor wafers. A plurality of surfaces are successively subjected to a polishing step, in which they are brought into contact with a polishing device. The polishing device contains a polishing-grain carrier with polishing grains, and the surfaces are moved relative to the polishing device. Material is removed from the surface by the polishing grains, which are fixed in the polishing-grain carrier and may become partially detached from the carrier material during the polishing operation. In each case one or more polishing steps is preceded by a conditioning step for regeneration of the polishing device. The polishing device and a conditioning surface of strong structure are brought into contact with one another and moved relative to one another, with the result that starting states of the polishing-device surface at a beginning of the individual polishing steps are comparable with one another.

Abstract: The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA′; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step.

Abstract: A substrate holder is described which has a movable plate elastically mounted inside a main body. With the substrate holder, a polishing operation can be performed in two basic operation modes corresponding to two different vertical end positions of the movable plate. In a first (downward) mode the movable plate stays in mechanical contact with the substrate whereas in a second (upward) mode an air cushion is generated in a chamber between the movable plate and the substrate for pressurizing the substrate onto the polishing pad.

Abstract: A process is described for the chemical mechanical machining of semiconductor wafers. A plurality of surfaces are successively subjected to a polishing step, in which they are brought into contact with a polishing device. The polishing device contains a polishing-grain carrier with polishing grains, and the surfaces are moved relative to the polishing device. Material is removed from the surface by the polishing grains, which are fixed in the polishing-grain carrier and may become partially detached from the carrier material during the polishing operation. In each case one or more polishing steps is preceded by a conditioning step for regeneration of the polishing device. The polishing device and a conditioning surface of strong structure are brought into contact with one another and moved relative to one another, with the result that starting states of the polishing-device surface at a beginning of the individual polishing steps are comparable with one another.

Abstract: A process for abrasive machining of surfaces of semiconductor wafers, in particular during the production of electronic memory elements, is described. In the process, a topography of the surfaces of a plurality of wafers is planarized by an at least partially mechanical route. In a further process step which takes place at a later stage, further material is removed from the planarization surfaces by the action of a liquid, chemical composition (etchback). After the planarization step and before the etchback step, a layer thickness measurement of the planarized layer is carried. The method is distinguished by the fact that the measurement results of the layer thickness measurement are used as the basis for the automatic selection or formulation of one of a plurality of chemical compositions and/or the time of action of a selected or formulated chemical composition for carrying out the etchback step.

Abstract: A substrate holder is described which has a movable plate elastically mounted inside a main body. With the substrate holder, a polishing operation can be performed in two basic operation modes corresponding to two different vertical end positions of the movable plate. In a first (downward) mode the movable plate stays in mechanical contact with the substrate whereas in a second (upward) mode an air cushion is generated in a chamber between the movable plate and the substrate for pressurizing the substrate onto the polishing pad.