Abstract: A memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (LUNs) and are associated with corresponding LUN queue groups. Each LUN queue group may include LUN queues that are each associated with a respective intra-LUN priority level that indicates a priority of a LUN queue within a LUN queue group. The LUN queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a LUN queue across LUN queue groups. A quantity of intra-LUN priority levels may be greater than a quantity of execution priority levels. A LUN scheduler may be configured to select and transfer commands from LUN queue groups to the execution queue group based on intra-LUN priority levels. A command executor may be configured to execute commands from the execution queue group based on execution priority levels.

Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.

Abstract: In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.

Abstract: A memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (LUNs) and are associated with corresponding LUN queue groups. Each LUN queue group may include LUN queues that are each associated with a respective intra-LUN priority level that indicates a priority of a LUN queue within a LUN queue group. The LUN queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a LUN queue across LUN queue groups. A quantity of intra-LUN priority levels may be greater than a quantity of execution priority levels. A LUN scheduler may be configured to select and transfer commands from LUN queue groups to the execution queue group based on intra-LUN priority levels. A command executor may be configured to execute commands from the execution queue group based on execution priority levels.

Abstract: Implementations described herein relate to suspending memory erase operations to perform high priority memory commands. In some implementations, a memory device may detect, while an active stage of an erase operation is being performed by the memory device, a pending memory command with a higher priority than the erase operation. The memory device may selectively suspend the active stage of the erase operation, to allow the pending memory command to be executed, based on the active stage of the erase operation that is being performed and/or a value of a suspend determination timer associated with suspending the active stage of the erase operation.

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.

Abstract: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address of a physical block stored on the memory device, wherein the physical address comprises an identifier of a memory device die; identify, based on block family metadata associated with the memory device, a block family associated with the physical block and the page number; determine a threshold voltage offset associated with the block family and the memory device die; compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and read, using the modified threshold voltage, data from a physical page identified by the page number within the physical block.

Abstract: An example method of generating an execution profile of a firmware module comprises: receiving an execution trace of a firmware module comprising a plurality of executable instructions, wherein the execution trace comprises a plurality of execution trace records, wherein each execution trace record of the plurality of execution trace records indicates a successful execution of an executable instruction identified by a program counter (PC) value; retrieving a first execution trace record of the plurality of execution trace records, wherein the first execution trace record comprises a first PC value; identifying a first executable instruction referenced by the first PC value; identifying a firmware function containing the first executable instruction; incrementing a cycle count for the firmware function by a number of cycles associated with the first executable instruction; and generating, using the cycle count, an execution profile of the firmware module.

Abstract: A die read counter and a block read counter are maintained for a specified block of a memory device. An estimated number of read events associated with the specified block is determined based on a value of the block read counter and a value of the die read counter. Responsive to determining that the estimated number of read events satisfies a criterion, a media management operation of one or more pages associated with the specified block is performed.

Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.

Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: A memory sub-system configured to predictively schedule the transfer of data to reduce idle time and the amount and time of data being buffered in the memory sub-system. For example, write commands received from a host system can be queued without buffering the data of the write commands at the same time. When executing a first write command using a media unit, the memory sub-system can predict a duration to a time the media unit becoming available for execution of a second write command. The communication of the data of the second command from the host system to a local buffer memory of the memory sub-system can be postponed and initiated according to the predicted duration. After the execution of the first write command, the second write command can be executed by the media unit without idling to store the data from the local buffer memory.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.