Patents by Inventor Mark J. Dechene
Mark J. Dechene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10761844Abstract: Disclosed embodiments relate to predicting load data. In one example, a processor a pipeline having stages ordered as fetch, decode, allocate, write back, and commit, a training table to store an address, predicted data, a state, and a count of instances of unchanged return data, and tracking circuitry to determine, during one or more of the allocate and decode stages, whether a training table entry has a first state and matches a fetched first load instruction, and, if so, using the data predicted by the entry during the execute stage, the tracking circuitry further to update the training table during or after the write back stage to set the state of the first load instruction in the training table to the first state when the count reaches a first threshold.Type: GrantFiled: June 29, 2018Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Manjunath Shevgoor, Mark J. Dechene, Stanislav Shwartsman, Pavel I. Kryukov
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Publication number: 20200004536Abstract: Disclosed embodiments relate to predicting load data. In one example, a processor a pipeline having stages ordered as fetch, decode, allocate, write back, and commit, a training table to store an address, predicted data, a state, and a count of instances of unchanged return data, and tracking circuitry to determine, during one or more of the allocate and decode stages, whether a training table entry has a first state and matches a fetched first load instruction, and, if so, using the data predicted by the entry during the execute stage, the tracking circuitry further to update the training table during or after the write back stage to set the state of the first load instruction in the training table to the first state when the count reaches a first threshold.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Manjunath SHEVGOOR, Mark J. DECHENE, Stanislav SHWARTSMAN, Pavel I. KRYUKOV
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Patent number: 10379864Abstract: In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.Type: GrantFiled: December 26, 2016Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: Chunhui Zhang, Seth H. Pugsley, Mark J. Dechene
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Patent number: 10228956Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.Type: GrantFiled: September 30, 2016Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Vineeth Mekkat, Mark J. Dechene, Zhongying Zhang, Jason Agron, Sebastian Winkel
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Publication number: 20180181402Abstract: In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.Type: ApplicationFiled: December 26, 2016Publication date: June 28, 2018Inventors: CHUNHUI ZHANG, SETH H. PUGSLEY, MARK J. DECHENE
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Publication number: 20180095765Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Vineeth Mekkat, Mark J. Dechene, Zhongying Zhang, Jason Agron, Sebastian Winkel
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Patent number: 9652236Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.Type: GrantFiled: December 23, 2013Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Srikanth T. Srinivasan, Mark J. Dechene, Yury N. Ilin, Justin M. Deinlein, Christine E. Wang, Matthew C. Merten
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Patent number: 9495159Abstract: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.Type: GrantFiled: September 27, 2013Date of Patent: November 15, 2016Assignee: Intel CorporationInventors: Mark J. Dechene, Srikanth T. Srinivasan, Matthew C. Merten, Tong Li, Christine E. Wang
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Publication number: 20150178077Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Inventors: SRIKANTH T. SRINIVASAN, MARK J. DECHENE, YURY N. ILIN, JUSTIN M. DEINLEIN, CHRISTINE E. WANG, MATTHEW C. MERTEN
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Publication number: 20150095627Abstract: In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Mark J. DECHENE, Srikanth T. SRINIVASAN, Matthew C. MERTEN, Tong LI, Christine E. WANG
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Publication number: 20140156977Abstract: Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.Type: ApplicationFiled: December 28, 2011Publication date: June 5, 2014Inventors: Mark J. Dechene, Matthew C. Merten, Sean P. Mirkes