Patents by Inventor Mark Kellogg
Mark Kellogg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937822Abstract: A device for creating a fistula between blood vessels operates in conjunction with a guidewire to locate and position itself so that it straddles both vessels and is able to draw them together. A fixing agent is released either from within the device or from an external needle, or both, into the procedural site. The fixing agent functions to hold the relative position of the two vessels, to seal the surrounding tissue so that any leaks that do occur don't spread into the tissue to create a hematoma, and to limit expansion of the fistula. After the vessels are in close proximity to each other and the fixing agent is applied, the device of the invention employs a cutting mechanism which opens a portal between the two vessels.Type: GrantFiled: July 6, 2020Date of Patent: March 26, 2024Assignee: AVENU MEDICAL, INC.Inventors: Seth Arnold Foerster, Brad Mathew Kellerman, Mark Andrew Ritchart, Justin Kellogg Mann
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Publication number: 20080016281Abstract: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.Type: ApplicationFiled: July 19, 2007Publication date: January 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Mark Kellogg, Warren Maule, Thomas Smith, Robert Tremaine
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Publication number: 20080016280Abstract: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.Type: ApplicationFiled: July 3, 2007Publication date: January 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Mark Kellogg, Warren Maule, Thomas Smith, Robert Tremaine
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Publication number: 20070255902Abstract: A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.Type: ApplicationFiled: July 5, 2007Publication date: November 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Kevin Kark, Mark Kellogg, Warren Maule
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Publication number: 20070250756Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.Type: ApplicationFiled: April 20, 2006Publication date: October 25, 2007Inventors: Kevin Gower, Bruce Hazelzet, Mark Kellogg, David Perlman
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Publication number: 20070204201Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.Type: ApplicationFiled: April 27, 2007Publication date: August 30, 2007Applicant: International Business Machines CorporationInventors: Kevin Gower, Bruce Hazelzet, Mark Kellogg, David Perlman
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Publication number: 20070204200Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.Type: ApplicationFiled: April 27, 2007Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Bruce Hazelzet, Mark Kellogg, David Perlman
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Publication number: 20070195572Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a pluality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.Type: ApplicationFiled: April 16, 2007Publication date: August 23, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Dreps, Frank Ferraiolo, Kevin Gower, Mark Kellogg, Roger Rippens
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Publication number: 20070001708Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.Type: ApplicationFiled: September 12, 2006Publication date: January 4, 2007Applicant: International Business Machines CorporationInventors: Claude Bertin, Wayne Ellis, Mark Kellogg, William Tonti, Jerzy Zalesinski, James Leas, Wayne Howell
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Publication number: 20060242541Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32 K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.Type: ApplicationFiled: April 20, 2006Publication date: October 26, 2006Inventors: Kevin Gower, Bruce Hazelzet, Mark Kellogg, David Perhnan
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Publication number: 20060236201Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.Type: ApplicationFiled: April 20, 2006Publication date: October 19, 2006Inventors: Kevin Gower, Bruce Hazelzet, Mark Kellogg, David Perlman
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Publication number: 20060190780Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.Type: ApplicationFiled: April 20, 2006Publication date: August 24, 2006Inventors: Kevin Gower, Bruce Hazelzet, Mark Kellogg, David Perlman
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Publication number: 20060136618Abstract: A multi-mode memory buffer device for use in various memory subsystem structures. The buffer device includes a packetized multi-transfer interface which is redriven to permit connection between a first memory assembly and cascaded memory assemblies. The buffer device also includes a memory interface adapted to connect to either a second memory assembly or directly to memory devices.Type: ApplicationFiled: July 30, 2004Publication date: June 22, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Mark Kellogg
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Publication number: 20060095620Abstract: A method for re-driving data in a memory subsystem. The method includes receiving controller interface signals and a forwarded interface clock associated with the controller interface signals at a memory module. The memory module is part of a cascaded interconnect system. The controller interface signals are sampled with the forwarded interface clock and the sampling results in the controller interface signals being latched into interface latches. The controller interface signals are then latched into local latches using a local clock on the memory module. The contents of the local latches along with the local clock are transmitted to an other memory module or controller in the cascaded interconnect system.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Applicant: International Business Machines CorporationInventors: Daniel Dreps, Frank Ferriaolo, Kevin Gower, Mark Kellogg, Roger Rippens
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Publication number: 20060095701Abstract: A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Kevin Kark, Mark Kellogg, Warren Maule
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Publication number: 20060095671Abstract: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Gower, Mark Kellogg, Warren Maule, Thomas Smith, Robert Tremaine
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Publication number: 20060036826Abstract: A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.Type: ApplicationFiled: July 30, 2004Publication date: February 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Dell, Kevin Gower, Kevin Kark, Mark Kellogg, Warren Maule
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Publication number: 20060036827Abstract: A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.Type: ApplicationFiled: July 30, 2004Publication date: February 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Dell, Frank Ferraiolo, Kevin Gower, Kevin Kark, Mark Kellogg, Warren Maule
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Publication number: 20060026349Abstract: A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORAITONInventors: Kevin Gower, Kevin Kark, Mark Kellogg, Warren Maule
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Publication number: 20060023482Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Dreps, Frank Ferriaolo, Kevin Gower, Mark Kellogg, Roger Rippens