Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, (c2) growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.

Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.

Abstract: A method for manufacturing a heterostructure for applications in the fields of electronics, photovoltaics, optics or optoelectronics, by implanting atomic species in a donor substrate so as to form an embrittlement area therein, assembling a receiver substrate on the donor substrate, wherein the receiver substrate has a larger thermal expansion coefficient than that of the donor substrate, detaching a rear portion of the donor substrate along the embrittlement area so as to transfer a thin layer of interest of the donor substrate onto the receiver substrate, and applying a detachment annealing after assembling and but before detaching, in order to facilitate the detaching. The detachment annealing includes the simultaneous application of a first temperature to the donor substrate and a second temperature different from the first to the receiver substrate; with the first and second temperatures being selected to reduce the tensile stress condition of the donor substrate.

Abstract: A method for manufacturing a heterostructure for applications in the fields of electronics, photovoltaics, optics or optoelectronics, by implanting atomic species in a donor substrate so as to form an embrittlement area therein, assembling a receiver substrate on the donor substrate, wherein the receiver substrate has a larger thermal expansion coefficient than that of the donor substrate, detaching a rear portion of the donor substrate along the embrittlement area so as to transfer a thin layer of interest of the donor substrate onto the receiver substrate, and applying a detachment annealing after assembling and but before detaching, in order to facilitate the detaching. The detachment annealing includes the simultaneous application of a first temperature to the donor substrate and a second temperature different from the first to the receiver substrate; with the first and second temperatures being selected to reduce the tensile stress condition of the donor substrate.

Abstract: A method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate. The method includes a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. The method also includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100° C. to 500° C.

Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate.

Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract: A method for etching a trench in a monocrystal silicon layer. The method includes providing a plasma processing system having a plasma processing chamber. The plasma processing system has a variable plasma generation source and a variable ion energy source with the variable plasma generation source being configured to be controlled independently of the variable ion energy source. The method further includes flowing an etchant source gas that includes O.sub.2, helium, and at least one of SF.sub.6 and NF.sub.3 into the plasma processing chamber. There is also included energizing both the variable plasma generation source and the variable ion energy source to form a plasma from the etchant source gas. Additionally, there is included employing the plasma to etch the trench.