Patents by Inventor Mark L. Rea

Mark L. Rea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9607822
    Abstract: Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 28, 2017
    Assignee: Lam Research Corporation
    Inventors: Bryan L. Buckalew, Mark L. Rea
  • Publication number: 20170011906
    Abstract: Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.
    Type: Application
    Filed: September 13, 2016
    Publication date: January 12, 2017
    Inventors: Bryan L. Buckalew, Mark L. Rea
  • Patent number: 9469912
    Abstract: Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: October 18, 2016
    Assignee: Lam Research Corporation
    Inventors: Bryan L. Buckalew, Mark L. Rea
  • Publication number: 20150303065
    Abstract: Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Applicant: Lam Research Corporation
    Inventors: Bryan L. Buckalew, Mark L. Rea
  • Patent number: 8470191
    Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: June 25, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
  • Patent number: 8158532
    Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 17, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
  • Publication number: 20090277867
    Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
    Type: Application
    Filed: November 20, 2006
    Publication date: November 12, 2009
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
  • Publication number: 20090280649
    Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
    Type: Application
    Filed: August 6, 2007
    Publication date: November 12, 2009
    Applicant: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
  • Patent number: 7449098
    Abstract: A disclosed form of mechanically assisted electroplating leads to a flat, thin, overburden. In one example, an accelerator is deposited on a copper surface and mechanically removed in a simplified CMP-like apparatus. The wafer is then plated in an electrolyte containing little or no accelerating additives.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: November 11, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan D. Reid, Mark L. Rea, Ismail T. Emesh, Henner W. Meinhold, John S. Drewery
  • Patent number: 7091134
    Abstract: In one embodiment, an integrated circuit (IC) fabrication material is dispensed from a print head by dividing its nozzles into several groups, and sequentially allowing each group to fire. The nozzles may be grouped based on the amounts of material they dispense. For example, the nozzles may be grouped by drop volume or drop mass. In one embodiment, an IC fabrication material is dispensed on a substrate by controlling a firing sequence of a nozzle to promote merging of material on the substrate. The firing sequence may also be altered to take into account the firing sequence of adjacent nozzles.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: August 15, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Henner W. Meinhold, Wayne Cai, Mark L. Rea, Sachin M. Chinchwadkar
  • Patent number: 6764168
    Abstract: In one embodiment, a sensor includes two plates that form a capacitor. A droplet passing between the plates changes the capacitance of the sensor, thereby triggering an amplifier coupled to the sensor to generate an output signal. The output signal is indicative of droplet characteristics and may be used to calibrate a mechanism that dispensed the droplet.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: July 20, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Henner W. Meinhold, Mark L. Rea, Sachin M. Chinchwadkar, Fred J. Chetcuti, John S. Drewery