Abstract: A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.

Abstract: A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously utilized in a microprocessor system comprising a central processing unit (CPU), a write back cache memory, dynamic random access memory (DRAM) main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer. In accordance with the method of operation, following a write access by the CPU, the CDC determines whether the write buffer is full and whether the cache line associated with this access has been modified, i.e. is "clean" or "dirty." In the event that the write buffer is full, or the cache line is dirty, the write operation proceeds in accordance with a write back mode of operation. However, if the write buffer in the DPU is not full, and the cache line is clean, the CDC writes the write data to both the cache line in cache memory, and the write buffer in the DPU.

Abstract: A concurrent cache line replacement method and apparatus for a high performance microprocessor system with a write-back cache memory is disclosed. The invention is advantageously utilized in a microprocessor system comprising a CPU, a write back cache memory, DRAM main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer capability. In accordance with the method of operation of the present invention, when a read access by the CPU results in a cache miss to a dirty cache line, the CDC concurrently initiates two operations. The CDC initiates the writing of the dirty line in the cache memory to a write buffer in the DPU, while concurrently, the CDC also initiates the reading of the new line from the DRAM main memory.