Abstract: A method of maintaining a cooling air path in an embedded computer chassis having a front side and a rear side includes providing a computing module portion and a fan module portion disposed adjacent to the computing module portion to accept a plurality of fan modules for drawing cooling air though the computing module portion. Cooling air is drawn into the front side of the embedded computer chassis through an air plenum disposed adjacent to the computing module portion, where the cooling air passes through the computing module portion, and where the cooling air is exhausted from the fan module portion through a rear side of the embedded computer chassis, thereby defining the cooling air path. An opening force is applied to a fan module portion cover to place the fan module portion cover in an open position, where the fan module portion cover is rotatable to the open position away and down from the fan module portion, where while in the open position the cooling air path is substantially interrupted.

Abstract: A method of latent fault checking a management network may include a management bus communicating management data for a computing module on the management network; a management controller managing the computing module; a master management controller operating the management bus; and a buffer module between the management bus and each of the management controller and the master management controller, where the buffer module is coupled to provide isolation for each of the management controller and the master management controller from the management bus. Prior to an active fault in the management network, a latent fault checking module is executed on the buffer module to determine if the latent fault checking module detects a latent fault on the buffer module.

Abstract: A method of latent fault checking a cooling module of an embedded computer chassis may include prior to detection of an active fault in the cooling module, performing a fan controller latent fault checking algorithm and a full-speed latent fault checking algorithm. The fan controller latent fault checking algorithm may include attempting to modify a fan speed in the cooling module via a fan controller module in the cooling module, and determining if a change in the fan speed is detected. The full-speed latent fault checking algorithm may include attempting to modify the fan speed via a full speed fan control circuit, bypassing the fan controller module, and determining if the change in the fan speed is detected. If the change in the fan speed is not detected in at least one of the fan controller latent fault checking algorithm and the full-speed latent fault checking algorithm, a latent fault in the cooling module of the embedded computer chassis may be indicated.

Abstract: A power distribution system and method may include a first power domain having a first plurality of power rails, a second power domain having a second plurality of power rails, where the first power domain is electrically independent of the second power domain, and a plurality of modules coupled to the first power domain and the second power domain, where each of the plurality of modules is coupled to one of the first plurality of power rails and one of the second plurality of power rails. The system may also include a plurality of mated pairs, where each of the plurality of modules is in only one of the plurality of mated pairs, and where each of the plurality of mated pairs is coupled to two separate of the first and second plurality of power rails.

Abstract: A power distribution system and method may include a first power domain having a first plurality of power rails, a second power domain having a second plurality of power rails, where the first power domain is electrically independent of the second power domain, and a plurality of modules coupled to the first power domain and the second power domain, where each of the plurality of modules is coupled to a unique set of one of the first plurality of power rails and one of the second plurality of power rails. The system may also include a plurality of mated pairs, where each of the plurality of modules is in only one of the plurality of mated pairs, where each of the plurality of mated pairs is coupled to four separate of the first and second plurality of power rails, and where each of the plurality of mated pairs is coupled to a unique set of the first plurality of power rails and the second plurality of power rails.

Abstract: A method of transporting an IP packet (136) from a receiving RapidIO node (102) over a RapidIO network (112) to a destination RapidIO node (104) includes the RapidIO domain receiving the IP packet and reading a destination IP address (273) of the IP packet, where the destination IP address corresponds to the destination RapidIO node. The receiving RapidIO node creates at least one RapidIO packet (135) and maps the destination IP address of the IP packet to a destination node ID (283) of the at least one RapidIO packet The destination node ID is placed into a RapidIO header (280) of the at least one RapidIO packet and at least a portion of the IP packet is encapsulated in the at least one RapidIO packet. The at least one RapidIO packet is communicated to the destination RapidIO node over the RapidIO network.

Abstract: A computing blade (102) having a USB electrical interface (106), includes a USB interface module (104) having a corresponding USB electrical interface (108), where the USB interface module is communicatively coupled to the computing blade through the USB electrical interface and the corresponding USB electrical interface, and wherein the USB interface module is non-embedded on the computing blade. A computing resource (110) is coupled to the USB interface module, where the computing resource communicates with the computing blade using a USB protocol (118). A mechanical retention device (112) secures the USB interface module to the computing blade, where the mechanical retention device permits user removal of the USB interface module from the computing blade.

Abstract: A method and apparatus include a real-time kernel (223) provides an emulated subset of WIN32 execution environment services (219). The real-time kernel initializes computer hardware (222) and software. Executable (206) is loaded into memory (214), and memory is allocated to executable, where the executable is programmed to execute in a WIN32 execution environment (116). The real-time kernel (223) permits execution of the executable in an emulated WIN32 execution environment (215), where the emulated WIN32 execution environment (215) utilizes the emulated subset of WIN32 execution environment services (219). The executable (206) operates real-time in the emulated WIN32 execution environment (215).

Abstract: In a method for switching between multiple system hosts (154,164,174,184) on a CompactPCI bus (110,120), a hot swap controller (166,186) provides to a special arbiter (820) a high priority request signal and the special arbiter (820) provides to the hot swap controller a grant signal only when the CompactPCI bus is idle. The hot swap controller (166,186) provides to the special arbiter (820) a float signal causing the special arbiter (820) to disable the system host signals, which include one or more grant signals for granting bus access to devices on the CompactPCI bus (110,120), one or more reset signals for resetting the devices, one or more interrupts and one or more clock signals provided to devices. The hot swap controller (166,186) transfers control of the CompactPCI bus (110,120) to a standby system host 154,164,174,184).

Abstract: In a method for swapping a system host board (150,160,170,180), when a failure is detected on a first system processor board (150), control of a first CompactPCI bus (110) is transferred from a first system processor board system host (154) to a first bridge board system host(164). In an active/standby configuration, control of a second CompactPCI bus (120) is transferred from a second bridge board system host (184) to a second system processor board system host (174), and control of the devices on the first CompactPCI bus (110) and second CompactPCI bus (120) is transferred from the first system processor (152) to the second system processor (172) without resetting any devices on the system.

Abstract: In a method for switching between multiple system processors (152,172) on a CompactPCI bus (110,120), when a standby system processor (172,152) determines a failure affecting an active system processor (152,172) on the CompactPCI bus (110,120), the standby system processor (172,152) places a special arbiter (820) in a one master mode. If the standby system processor (172,152) determines that a device is at risk of performing a destructive action, the standby system processor (172,152) quiesces the device. The standby system processor (172,152) then places the special arbiter (820) in a multiple master mode.

Abstract: A multiconfiguration backplane (100) can be configured in four different configurations: dual, extended, active/standby and active/active. The multiconfiguration backplane (100) has a first COMPACT PCI bus (110) with a first system processor slot (112), a first bridge slot (114), and a first set of one or more input/output slots (116). The multiconfiguration backplane has a second COMPACT PCI bus (120) with a second system processor slot (122), a second bridge slot (124), and a second set of one or more input/output slots (126). A first cross connection (130) is between the first system processor slot (112) and the second bridge slot (124), and a second cross connection (140) is provided between the second system processor slot (122) and the first bridge slot (114). Preferably, the first cross connection is a first local PCI bus and the second cross connection is a second local PCI bus.