Abstract: Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that impact timing; selecting an element of the circuit design that dominates circuit delay in the timing model; determining a delay sensitivity of each of a set of derived process parameters (Vj) for the element that are linear combinations of the process parameter variations (Pi); and selecting only those derived process parameters with a high sensitivity for use in the statistical model. The invention simplifies the statistical model and reduces the number of calculations require for timing analysis. A method of performing a timing analysis using the simplified statistical model is also disclosed.

Abstract: A method, system and program product are disclosed that create new shapes at detected shape overlaps and includes those new shapes during routing and net checking when the new shapes require a larger space than any of the overlapping shapes. The invention thus detects and prevents spacing errors without the expense of time consuming design rule checking (DRC), facilitating early detection and prevention of errors.

Abstract: A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks 110; positioning a temporary reference insertion point (TIP) 120; grouping the sinks together with structured clock buffers (SCBs) in a set of levels 140; and moving the SCBs to improve symmetry of the tree 150. The SCBs may be of several sizes and may be positioned horizontally 42 or vertically 45 and moved within limits 46 to permit the program to calculate a complete tree.