Abstract: A system for controlling contrast of a liquid crystal display is provided by means of a parallel network of resistors. A processor controls general operations of the system and is configured to determine a desired contrast setting of the LCD. The processor is operative to assign a binary value corresponding to the desired contrast setting. A binary decoder is operatively coupled to the processor and is configured to receive the binary value of x bits from the processor. A circuit includes N number of resistors (N being an integer greater than x) configured to be coupled in parallel to effect a plurality of cumulative parallel resistance values for the circuit. The circuit is operatively coupled to the binary decoder. The binary decoder selectively combines the resistors to effect a specific cumulative parallel resistance value corresponding to the desired contrast setting.