Abstract: An analog-to-digital conversion module, QADC (1), and method minimize software involvement by providing a pause capacility. Each queue in the QADC (1) has one or more Conversion Command Words, CCWs (82), in a Conversion Command Word Table (62). Each conversion command word, CCW (82), has a Pause bit which can be used to create multiple sub-queues of A/D conversions without requiring the use of interrupts. The Pause bit can be used to place a queue in a pause state. When a queue enters a pause state, the scanning of CCWs (82) is stopped. The queue must then receive a trigger in order for the scanning of CCWs (82) to continue again.

Abstract: A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) should execute an initialization operation or function in a normal mode of operation. The memory system (16) begins execution of the initialization operation of the system (10) in response to both a logic value of a reset signal and a value of an address transferred by an address bus. The memory system (16) automatically terminates execution of the initialization operation in response to the value of the address transferred by the address bus.

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Abstract: In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must arbitrate for the interrupt slot. If no arbitration occurs the interrupt request was spurious and bus error is activated.

Abstract: An analog-to-digital conversion system module and method provides programmable times for sampling analog input signals. Software involvement is minimized by providing a command word which includes information specifying a sample time. The command word may be stored in a register or memory table. The command word or words may specify the conversion time per analog input channel or group of channels, and per conversion or conversion sequence. In one embodiment a control table comprises a plurality of conversion command words (CCW's). Each CCW designates conversion parameters including the input sample time.

Abstract: A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

Abstract: A serial peripheral interface achieves compatibility with devices having previous such interfaces while significantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

Abstract: A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. The starting address registers, and enable registers which control whether each patch block is placed in the memory map, are programmable under control of the microcomputer's CPU. Newly programmed values in these registers are not effective to alter the memory map until a reset sequence enables a latch. In particular embodiments, patch blocks may overlie mask ROM, internal EPROM and/or EEPROM, external memory or devices or any other desireable portion of the memory map.