Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: A computer-implemented method for managing a memory control unit includes receiving a command at the memory control unit. The command includes a command type that either requires or does not require buffering resources. The method further includes determining, via the memory control unit, a number of available memory tags from a first set of memory tags that are associated with the buffering resources. The method includes determining, via the memory control unit, a number of available memory tags from a second set of memory tags that are not associated with the buffering resources. The method also includes dynamically adjusting, via the memory control unit, assignment of memory tags for use in the second set of memory tags based on the command type, the number of available memory tags from the first set of memory tags, and the number of available memory tags from the second set of memory tags.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: A computer-implemented method for managing a memory control unit includes receiving a command at the memory control unit. The command includes a command type that either requires or does not require buffering resources. The method further includes determining, via the memory control unit, a number of available memory tags from a first set of memory tags that are associated with the buffering resources. The method includes determining, via the memory control unit, a number of available memory tags from a second set of memory tags that are not associated with the buffering resources. The method also includes dynamically adjusting, via the memory control unit, assignment of memory tags for use in the second set of memory tags based on the command type, the number of available memory tags from the first set of memory tags, and the number of available memory tags from the second set of memory tags.

Abstract: Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.

Abstract: Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.

Abstract: A computer implemented method for early data delivery prior to error detection completion in a memory system includes receiving a frame of a multi-frame data block at a memory control unit interface. A controller writes the frame to a buffer control block in a memory controller nest domain. The frame is read from the buffer control block by a cache subsystem interface in a system domain prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame by an error detector in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to a correction pipeline in the system domain. The intercept signal indicates that error correction is needed prior to writing data in the frame to a cache subsystem.

Abstract: Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.

Abstract: Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.

Abstract: A computer implemented method for early data delivery prior to error detection completion in a memory system includes receiving a frame of a multi-frame data block at a memory control unit interface. A controller writes the frame to a buffer control block in a memory controller nest domain. The frame is read from the buffer control block by a cache subsystem interface in a system domain prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame by an error detector in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to a correction pipeline in the system domain. The intercept signal indicates that error correction is needed prior to writing data in the frame to a cache subsystem.

Abstract: Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage.

Abstract: Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.

Abstract: Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.

Abstract: Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.

Abstract: Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.

Abstract: Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage.

Abstract: A method of decoding a bitstream having an embedded clock, where the clock reference data is recovered from the bit stream. The clock reference data is combined, typically subtracted, from the system time clock to generate a result. This result is input to a pulse width modulator to form a pulse train, which is used to generate an input to a timing device.