Abstract: A method for operating a phased array antenna for a wireless communication system serving an area in which communications demands from a plurality of mobile communication devices change as a function of time, the method involving: for each time of a plurality of successive times, (1) obtaining information indicative of a total mobile communications demand density as a function of beam direction for that time; and (2) with the phased array antenna, electronically generating a communication beam directed in a direction for which total mobile communications demand density is high for that time relative to other beam directions.

Abstract: A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 &mgr;m gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n+/p+ dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.

Abstract: Logic devices of the present invention have one or more MOSFETs that are configured to operate in logic circuits, where voltages applied to the source and drain of each MOSFET are treated as logic inputs to the circuit and the resulting substrate current is treated as the logic output of the circuit. In one implementation, a MOSFET is configured in a circuit to operate as an XOR gate where a load resistor between the substrate and ground converts the substrate current into an output voltage. A sample-and-hold circuit samples and holds the output voltage to isolate the XOR gate thereby allowing DC power dissipation to be reduced. In another implementation, three MOSFETs are configured to operate as an "ORNAND" logic device that performs the logical addition of the OR function and the NAND function.

Abstract: Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

Abstract: Disclosed are a novel logic element (designated NORAND), and articles that comprise the element. Exemplarily, the NORAND element comprises three input terminals and an output terminal. If one of the input terminals is at logic 0 then the element functions as a logic NOR unit, and if the terminal is at logic 1 the element functions as a logic AND unit. The novel element thus makes possible reprogrammable and/or self-organizing logic circuits. The NORAND element can be realized with a single active semiconductor device, exemplarily a real space transfer (RST) device.