Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Abstract: A differential communication system includes a first differential communication device including a differential transmitter, a second differential communication device including a differential receiver, and a differential isolator coupling the differential transmitter to the differential receiver. The differential receiver includes a comparator operative to develop waveform region information from the received waveform, a filter adapted to remove noise from the received waveform using the waveform region information, and an adaptive sampler adapted to adjust a received waveform sampling point after it has been filtered.

Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.

Abstract: A differential communication system includes a first differential communication device including a differential transmitter, a second differential communication device including a differential receiver, and a differential isolator coupling the differential transmitter to the differential receiver. The differential receiver includes a comparator operative to develop waveform region information from the received waveform, a filter adapted to remove noise from the received waveform using the waveform region information, and an adaptive sampler adapted to adjust a received waveform sampling point after it has been filtered.

Abstract: A Hall-effect element includes an isolating layer and an active layer of a first electrical conductivity type disposed on the isolating layer, the active layer having a surface. A first set of contacts is disposed in contact with the surface along a first axis, and a second set of contacts is disposed in contact with the surface along a second axis transverse to the first axis. An insulating layer is disposed on the surface. A metal control field plate is disposed on the insulating layer and is coupleable to a voltage source to control the accumulation of charge carriers at the surface of the active layer to vary the resistance of the active layer. Also, a method is provided for reducing null offset in a Hall-effect element.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: A magnetic sensor circuit provides current sources that create a feedback loop for an amplifier of one magnetically sensitive component in order to maintain the sensor output and the corresponding amplifier input at a first preselected magnitude which can be generally equal to zero. The other current source maintains a generally identical current as a reference against which the output of another magnetically sensitive component is compared. The magnetically sensitive components can be Hall effect elements, indium antimonide sensors or magnetoresistive elements. The output of the circuit is representative of the difference between the magnetic field intensities imposed on the first and second magnetically sensitive components.

Abstract: A pressure sensor is provided in which the pressure sensing components are isolated from a portion of an attached buffer member which is connected to a fluid conduit. The offset characteristic of the pressure sensor isolates stress from being transmitted between an attached external fluid conduit and the sensitive components of the pressure sensor. One embodiment of the pressure sensor solders a fluid conduit structure to a buffer member that is attached to a pressure sensor die. An alternative embodiment of the present invention avoids the need for making solder connections between the sensor structure and external components by utilizing elastomeric conductors and pressure seals in association with the pressure sensor composite structure and first and second housing structures. These elastomeric conductors also provide improved stress isolation. The housing structures are used to compress to the seal and the elastomeric conductor against selected portions of the composite sensor.

Abstract: A resistor formed in the same epitaxial layer of semiconductor material in which a Hall element is formed is used to provide a temperature dependent voltage source which is inversely proportional to the resistance of a temperature sensitive load resistor on the Hall element output. A current mirror circuit is used to apply a current proportional to the current through the epitaxial layer resistor to the load resistor so that the voltage across through the load resistor varies in a direct relationship with the sensitivity of the Hall element.

Abstract: A structure for an Integrated Injection Logic (I.sup.2 L) gate is disclosed in which gate gain .alpha.*.beta. is improved and leakage current at the silicon-silicon dioxide interface is reduced. A plug of highly doped material is interposed between the emitter and the collector of the lateral transistor to accomplish these goals.

Abstract: A semiconductor logic circuit utilizing level shifting of input transistors away from a reference voltage level but shifting the output toward the reference voltage level to increase noise margin. The input signals may switch both the input transistors and the output transistors.