Patents by Inventor Mark R. Thomann
Mark R. Thomann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7562268Abstract: A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test data, and the test data is produced at a single output on edges of a clock signal.Type: GrantFiled: December 8, 2005Date of Patent: July 14, 2009Assignee: Micron Technology, Inc.Inventors: Mirmajid Seyyedy, Mark R. Thomann
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Patent number: 7251715Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.Type: GrantFiled: April 27, 2006Date of Patent: July 31, 2007Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Patent number: 7093095Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.Type: GrantFiled: December 9, 2003Date of Patent: August 15, 2006Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Patent number: 6976195Abstract: A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test data, and the test data is produced at a single output on edges of a clock signal.Type: GrantFiled: January 29, 1999Date of Patent: December 13, 2005Assignee: Micron Technology, Inc.Inventors: Mirmajid Seyyedy, Mark R. Thomann
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Patent number: 6954388Abstract: A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.Type: GrantFiled: August 31, 2004Date of Patent: October 11, 2005Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Patent number: 6901013Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.Type: GrantFiled: June 5, 2001Date of Patent: May 31, 2005Assignee: Micron Technology, Inc.Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
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Patent number: 6836437Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.Type: GrantFiled: August 28, 2003Date of Patent: December 28, 2004Assignee: Micron Technology, Inc.Inventors: Wen Li, Mark R. Thomann, Daniel R. Loughmiller, Scott Schaefer
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Patent number: 6809990Abstract: A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.Type: GrantFiled: June 21, 2002Date of Patent: October 26, 2004Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Patent number: 6809974Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.Type: GrantFiled: August 29, 2002Date of Patent: October 26, 2004Assignee: Micron Technology, Inc.Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
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Patent number: 6763444Abstract: A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration.Type: GrantFiled: May 8, 2001Date of Patent: July 13, 2004Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Christopher K. Morzano, Wen Li
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Publication number: 20040117543Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.Type: ApplicationFiled: December 9, 2003Publication date: June 17, 2004Applicant: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Publication number: 20040042282Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.Type: ApplicationFiled: August 28, 2003Publication date: March 4, 2004Inventors: Wen Li, Mark R. Thomann, Daniel R. Loughmiller, Scott Schaefer
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Patent number: 6694416Abstract: Systems, devices, and methods. A double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.Type: GrantFiled: September 2, 1999Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Publication number: 20030235106Abstract: A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.Type: ApplicationFiled: June 21, 2002Publication date: December 25, 2003Applicant: Micron Technology, Inc.Inventors: Mark R. Thomann, Wen Li
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Patent number: 6665219Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.Type: GrantFiled: July 22, 2002Date of Patent: December 16, 2003Assignee: Micron Technology, Inc.Inventors: Wen Li, Mark R. Thomann, Daniel R. Loughmiller, Scott Schaefer
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Publication number: 20020191462Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.Type: ApplicationFiled: August 29, 2002Publication date: December 19, 2002Applicant: Micron Technology, Inc.Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
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Publication number: 20020181296Abstract: A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Inventors: William Jones, Wen Li, Mark R. Thomann, Timothy B. Cowles, Daniel R. Loughmiller
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Publication number: 20020181299Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.Type: ApplicationFiled: July 22, 2002Publication date: December 5, 2002Inventors: Wen Li, Mark R. Thomann, Daniel R. Loughmiller, Scott Schaefer
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Patent number: 6487207Abstract: An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.Type: GrantFiled: December 6, 1999Date of Patent: November 26, 2002Assignee: Micron Technology, Inc.Inventor: Mark R. Thomann
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Publication number: 20020169922Abstract: A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration.Type: ApplicationFiled: May 8, 2001Publication date: November 14, 2002Inventors: Mark R. Thomann, Christopher K. Morzano, Wen Li