Abstract: A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.

Abstract: Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer.

Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.

Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.

Abstract: Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen concentration; and adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer includes a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the second region having a second oxygen concentration and a second nitrogen concentration, in which the second nitrogen concentration exceeds the first nitrogen concentration, provided that the second nitrogen concentration does not exceed the second oxygen concentration. In one embodiment, the first nitrogen concentration is substantially zero.

Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

Abstract: A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls.

Abstract: A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.

Abstract: An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

Abstract: A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly dielectric layer can be formed in-situ within a single deposition tool. In certain embodiments, the resulting single interpoly dielectric layer can be made thinner and/or can be formed to provide improved dielectric characteristics when compared to a conventional oxide-nitride-oxide (ONO) interpoly dielectric layer that has three separate and unique layers. Thus, the single interpoly dielectric layer is highly desirable for use in reduced-size semiconductor devices and/or semiconductor devices requiring improved data retention capabilities, such as non-volatile memory cells.

Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.