Patents by Inventor Mark Ronald Sikkink
Mark Ronald Sikkink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220030091Abstract: Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.Type: ApplicationFiled: June 7, 2021Publication date: January 27, 2022Inventors: Mark Ronald Sikkink, Randal Steven Passint, Joseph Martin Placek, Russell Leonard Nicol
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Patent number: 11032397Abstract: Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.Type: GrantFiled: June 17, 2015Date of Patent: June 8, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Mark Ronald Sikkink, Randal Steven Passint, Joseph Martin Placek, Russell Leonard Nicol
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Patent number: 10243853Abstract: An apparatus and method detects trapped data at an intermediate node in a network path between a source node and a destination node, and re-routes that data to a downstream intermediate node in the network path via an alternate network path. An apparatus and method may include a virtualized physical interface, and may redirect the trapped data through a system's packet switched network, or through a system's flit switched network.Type: GrantFiled: November 21, 2016Date of Patent: March 26, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Russell Leonard Nicol, Joseph Martin Placek, Mark Ronald Sikkink
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Publication number: 20180145913Abstract: An apparatus and method detects trapped data at an intermediate node in a network path between a source node and a destination node, and re-routes that data to a downstream intermediate node in the network path via an alternate network path. An apparatus and method may include a virtualized physical interface, and may redirect the trapped data through a system's packet switched network, or through a system's flit switched network.Type: ApplicationFiled: November 21, 2016Publication date: May 24, 2018Inventors: Russell Leonard Nicol, Joseph Martin Placek, Mark Ronald Sikkink
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Patent number: 9852096Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.Type: GrantFiled: March 25, 2014Date of Patent: December 26, 2017Assignee: Hewlett Packard Enterprise Development LPInventors: Mark Ronald Sikkink, John Francis De Ryckere, Joseph Martin Placek, Karen Rae Beighley
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Publication number: 20160373557Abstract: Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.Type: ApplicationFiled: June 17, 2015Publication date: December 22, 2016Inventors: Mark Ronald Sikkink, Randal Steven Passint, Joseph Martin Placek, Russell Leonard Nicol
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Patent number: 9252812Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.Type: GrantFiled: March 28, 2014Date of Patent: February 2, 2016Assignee: Silicon Graphics International Corp.Inventors: Mark Ronald Sikkink, John Francis De Ryckere
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Publication number: 20150278040Abstract: A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.Type: ApplicationFiled: March 25, 2014Publication date: October 1, 2015Applicant: Silicon Graphics International Corp.Inventors: Mark Ronald Sikkink, John Francis De Ryckere, Joseph Martin Placek, Karen Rae Beighley
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Publication number: 20150280746Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: Silicon Graphics International Corp.Inventors: Mark Ronald Sikkink, John Francis De Ryckere
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Patent number: 7333516Abstract: The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is selected and a second latch for receiving data from the first domain when the second latch is selected. A third latch is provided for transferring data from either the first latch or the second latch to the second domain when the second domain is clocked.Type: GrantFiled: July 20, 2000Date of Patent: February 19, 2008Assignee: Silicon Graphics, Inc.Inventors: Mark Ronald Sikkink, William A. Huffman, Vernon W. Swanson, Nan Ma, Randal S. Passint
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Patent number: 6920526Abstract: The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One embodiment of the invention includes a dual bank FIFO that comprises a first bank of memory elements operable to buffer memory data and a second bank of memory elements operable to buffer memory data. Write control address logic is operable to store selected memory data in memory elements with selected addresses within a bank of memory elements, and write control timing logic is operable to selectively grant write access to the banks of memory elements at predetermined time. Also, read control logic operable to read data stored in the first and second banks.Type: GrantFiled: July 20, 2000Date of Patent: July 19, 2005Assignee: Silicon Graphics, Inc.Inventors: Mark Ronald Sikkink, Nan Ma
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Patent number: 6726505Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.Type: GrantFiled: August 29, 2002Date of Patent: April 27, 2004Assignee: Silicon Graphics, Inc.Inventors: Stephen Cermak, III, Jeffrey S. Conger, David Paul Gruber, Thomas Alex Crapisi, Stephen A. Bowen, Steven Shafer, Mark Ronald Sikkink
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Publication number: 20030077925Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.Type: ApplicationFiled: August 29, 2002Publication date: April 24, 2003Applicant: Silicon Graphics, Inc.Inventors: Stephen Cermak, Jeffrey S. Conger, David Paul Gruber, Thomas Alex Crapisi, Stephen A. Bowen, Steven Shafer, Mark Ronald Sikkink
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Patent number: 6518812Abstract: A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.Type: GrantFiled: July 20, 2000Date of Patent: February 11, 2003Assignee: Silicon Graphics, Inc.Inventors: Mark Ronald Sikkink, Nan Ma
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Patent number: 6496048Abstract: A system and method of controlling delay in a delay line. In a delay line having a system mode and an oscillator mode, wherein the delay line delays a signal as a function of a delay code, the method comprises setting the delay code, placing the delay line in oscillator mode, determining frequency of oscillation of the delay line, comparing the frequency of oscillation to a target frequency and adjusting the delay code until the frequency of oscillation of the delay line is substantially equal to the target frequency.Type: GrantFiled: July 20, 2000Date of Patent: December 17, 2002Assignee: Silicon Graphics, Inc.Inventor: Mark Ronald Sikkink
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Patent number: 6441666Abstract: A system and method of generating a clock signal as a function of a system clock. A plurality of overlapping phases are generated and two or more of the overlapping phases are combined to form the clock signal.Type: GrantFiled: July 20, 2000Date of Patent: August 27, 2002Assignee: Silicon Graphics, Inc.Inventors: Vernon W. Swanson, Mark Ronald Sikkink
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Patent number: 5694028Abstract: A method and apparatus for adjusting power supplied to a device when the device has a first and a second power input. A first voltage level and a ground potential are provided and a second voltage level is created as a function of the first voltage level. The second voltage level is then buffered with a power transistor and, if the second voltage level is needed for a particular device, the buffered second voltage level is selectively applied to the device. The circuit is disabled when the second voltage supply is not needed.Type: GrantFiled: May 20, 1996Date of Patent: December 2, 1997Assignee: Cray Research, Inc.Inventors: Richard B. Salmonson, Robert J. Greener, Mark Ronald Sikkink, Robert J. Lutz, Max C. Logan, Richard G. Finstad