Abstract: Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.

Abstract: Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer pats are determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel.

Abstract: In a motion compensation engine, a number of blocks are provided for re-ordering motion vector (MV) reference positions prior to fetch. An MV Sort & Group block outputs MVs one at a time to a Decomposer block. The Decomposer block takes each MV and decomposes it into a series of DRAM read commands consisting of DRAM addresses. This rectangular region is divided into pixel words, which correspond to addressable DRAM words. The addresses are then sent to an Overlap Remover block, which comprises a bitmap corresponding to the DRAM addresses sent to it from the Decomposer block. Before a group is received, the bitmap is cleared by setting all coordinates to “0”. Each address received causes the Overlap Remover to set a bit to “1” in the bitmap which corresponds to a relative (x,y) coordinate within a small bounded rectangular region. Addresses received within a group, which are the same as previous addresses, are overlapping addresses and the corresponding bit will simply remain set to “1”.

Abstract: Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.

Abstract: Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device is identified and allocated for storage of data associated with the user-entered data declaration.

Abstract: A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

Abstract: In a motion compensation engine, a number of blocks are provided for re-ordering motion vector (MV) reference positions prior to fetch. An MV Sort & Group block outputs MVs one at a time to a Decomposer block. The Decomposer block takes each MV and decomposes it into a series of DRAM read commands consisting of DRAM addresses. This rectangular region is divided into pixel words, which correspond to addressable DRAM words. The addresses are then sent to an Overlap Remover block, which comprises a bitmap corresponding to the DRAM addresses sent to it from the Decomposer block. Before a group is received, the bitmap is cleared by setting all coordinates to “0”. Each address received causes the Overlap Remover to set a bit to “1” in the bitmap which corresponds to a relative (x,y) coordinate within a small bounded rectangular region. Addresses received within a group, which are the same as previous addresses, are overlapping addresses and the corresponding bit will simply remain set to “1”.