Abstract: A power loss detector for generating a signal indicating the need to switch from a main power supply to an auxiliary power supply responsive to detecting that the main power supply has dropped below a predetermined threshold.

Abstract: A buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used to interface with multiple voltage levels. The circuit uses a protection transistor in which the gate is controlled by a logic circuit having the mixed voltages as inputs. It is particularly useful on CMOS semiconductor chips that interface with multiple voltage levels which are required to conform to a specification allowing voltage levels to be powered down.

Abstract: An integrated circuit ESD protection technique includes a protection circuit having a series resistor-capacitor circuit connected between power supply bondpads. The resistor-capacitor circuit provides a desired time constant for control of active drive circuitry that controls a protective transistor also connected between the bondpads. The time constant is chosen to be short enough to prevent conduction of the protective transistor during normal operation and power-up, while still allowing conduction of the protective transistor during the initial phase of an ESD event. A feedback resistor is connected in parallel with the active circuitry, thereby lengthening the time that the protective transistor conducts during an ESD event. In this manner, the ESD current is more completely conducted through the protective circuitry, so that the level of protection is increased.

Abstract: An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.

Abstract: An application specific integrated circuit (ASIC) clock driver is built under the power supply second level (metal2) buses, with the p-channel and n-channel transistors lying under the V.sub.DD and V.sub.SS buses, respectively. The transistor gates in the clock driver are placed orthogonally with respect to the transistor gates in the polycells. This allows for easy access to the metal2 bus and eliminates the need for the clock driver transistors to "add to" the current flowing through the first level (metal1) V.sub.DD /V.sub.SS buses in the polycell row. Therefore, electromigration concerns are reduced for: (1) the core logic polycells; (2) within the clock driver itself; and (3) on the metallization of the output of the clock driver, since the clock driver typically drives large capacitive loads. The orthogonal layout scheme also allows for full contact of the transistors source and drain regions to the corresponding metal bus, providing for low series resistance.

Abstract: A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V.sub.SS), and the underlying semiconductor region is connected to the positive power supply conductor (V.sub.DD). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.

Abstract: Integrated circuits implemented in insulated gate (e.g., CMOS) technology have been protected from electrostatic discharge (ESD) by a metal gate field effect transistor. It has been recognized that a "parasitic" bipolar transistor exists in parallel with the metal gate device. Surprisingly, superior protection is obtained by omitting the metal gate, thereby relying only on the avalanche breakdown of the bipolar device for the opposite-polarity protection. It is postulated that the field effect of the metal gate device undesirably restricted the current flow in the prior art technique. The inventive technique may be advantageously implemented using a diode rather than a transistor as the protective element.

Abstract: An integrated circuit has an input pad protected from electrostatic discharge by two diodes located under the periphery of the pad. One of the diodes is typically formed in a n-tub, and the other in a p-tub. The boundary between the tubs is located in a region not overlaid by the exposed portion of the pad in one embodiment. An input resistor is optionally included between the pad and the input circuitry for additional ESD protection.