Abstract: Systems and methods facilitate accurate and rapid simulation of software by periodically saving simulation states and design stimuli for use as a replay model. Divergences from the stored information may be detected during subsequent re-executions, which can in turn be run using the saved stimuli and states.

Abstract: Systems and methods facilitate accurate and rapid simulation of software by periodically saving simulation states and design stimuli for use as a replay model. Divergences from the stored information may be detected during subsequent re-executions, which can in turn be run using the saved stimuli and states.

Abstract: System and methods for generating a software object that simulates the operation of a hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the electronic device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).

Abstract: System and methods high-performance simulation of the operation of a hardware device. A software object, based on a register transfer level description of the device written in a hardware description language, such as Verilog, is used for the simulation. The invention uses global analysis techniques (i.e., analysis of the design of the electronic device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).

Abstract: System and methods for simulating a software object generated from a hardware description of an electronic device. The hardware description is a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the hardware device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).

Abstract: System and methods for analyzing the design of the hardware device as a whole, rather than in fragments. This provides a basis for a high-performance simulation of the hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).

Abstract: Access is restricted to software objects that simulate the operation of electronic devices from register transfer level descriptions thereof. Objects are initially provided in an inaccessible state, typically as object code. A “player” module mediates user access to the simulation object, allowing the user to link to it and otherwise perform the simulation it encodes, but only in response to satisfaction of one or more authorization criteria. The nature of these criteria depend on the reason for the restriction and the party benefited.

Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased.

Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased.

Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased.