Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: A system and method for resizing an original image into a resized image is provided. The system processes the luminance channel and the chrominance channels (Cb and Cr) of the original image separately. The original image is divided into original sub-blocks of appropriate size. Each original sub-block may be processed into a corresponding resized sub-block. Only the luminance and chrominance data from one of the original sub-blocks may be used to create a corresponding resized sub-block, thus no overlap techniques need be employed. The system and method resizes the original sub-blocks into the resized sub-blocks without the use of multipliers.

Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

Abstract: The present invention provides an auxiliary catalytic converter having a back pressure relief device being disposed after the main catalytic converter or after the muffler system which further reduces vehicle exhaust emissions from exhaust emission systems and that will meet the more stringent emission requirements of state and federal government regulations. The auxiliary catalytic converter includes a ceramic or steel housing of relatively small size, having a diameter in the range of 1 inch to 8 inches and a length of 4 inches to 11 inches. The housing includes a matrix core of catalytic layered materials which react with the gaseous exhaust emission pollutants, such as NO.sub.x, NHMC, HC, and CO. These pollutants are further reduced and oxidized by the auxiliary catalytic converter using typical catalytic materials of platinum, palladium, rhodium, or the like contained within the honeycombed or meshed layers of the matrix core.

Abstract: A catalytic converter for a tailpipe which further reduces vehicle exhaust emissions from exhaust emission systems and that will meet the more stringent emission requirements of state and federal government regulations. The tailpipe catalytic converter includes a ceramic or steel housing which includes a matrix core of catalytic layered materials which react with the exhaust emission pollutants, such as NO.sub.x, NMHC, HC, and CO. These pollutants are further reduced and oxidized by the catalytic converter in the tailpipe by the typical catalytic materials of platinum, palladium, rhodium, or the like contained within the honeycombed or meshed layers of the matrix core. The catalytic converter is lodged within the interior of the tailpipe adjacent the open end or as an extension to the end of the tailpipe. The tailpipe catalytic converter is held in place by any suitable device, such as a clamp, mounting screws, or mounting brackets.

Abstract: An adder which reduces signal propagation delay experienced by conventional adders by calculating bitwise carries and utilizing these bitwise carries as non-selecting inputs. In a preferred embodiment, the adder includes three primary circuits. The first circuit for generating propagate and generate signals based on its two inputs. The second circuit uses the propagate and generate signals in combination with a global carry-in signal to produce bitwise carries based on the Kogge-Stone Parallel Algorithm. These bitwise carries in combination with bit sums of the first and second digital inputs are used to calculate a plurality of real bit sums corresponding to the sum of these digital inputs.

Abstract: An integrated circuit device performing arithmetic operations on a plurality of digital inputs to produce an effective address and a linear address in a single operation. The integrated circuit device comprises a first circuit, a first adder circuit and a second adder circuit. The first circuit performs logical operations on the plurality of digital inputs to produce a first group of output signals and a second group of output signals. The first adder circuit, coupled to the first circuit, performs a first set of arithmetic operations on the first group of output signals to produce an effective address. Concurrently, the second adder circuit, coupled to the first circuit and in parallel with the second adder circuit, performs a second set of arithmetic operations on the second group of output signals to produce a linear address.

Abstract: An integrated circuit device performing arithmetic operations on a plurality of digital inputs to produce an Effective Address and a Linear Address in parallel. The integrated circuit device comprises a first, second and third circuit. The first circuit includes a first adding circuit performs logical operations on the plurality of digital inputs (segment address, scaled index, displacement and segment base) to produce a first plurality of output signals for use in producing the Effective Address and another plurality of output signals to produce an uncorrected Linear Address. The uncorrected Linear Address, if accurate, should be equivalent to the arithmetic sum of the Effective Address and the segment base.

Abstract: A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.