Abstract: A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

Abstract: A method and apparatus for selectively causing each bank of a number of banks of DRAMs of a DRAM memory card to enter into the self-refresh mode without affecting the operation of any other bank. In the computer system incorporating the SIMM or DIMM type DRAM cards, each bank of memory on each card has a RAS signal specific to that specific bank. One or more CAS signals are supplied across all of the memory banks, on all cards. Thus, each memory bank is accessed separately for a read/write operation by the RAS becoming active before the CAS becomes active; and refresh takes place by the CAS signal becoming active before the RAS signal becomes active. The number of clock cycles or refresh cycles between active RAS signals to each memory bank are counted.

Abstract: A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise.

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

Abstract: A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency.

Abstract: A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.

Abstract: A synchronous dynamic random access memory subsystem includes two banks of connectors for receiving single or dual in-line memory modules. A clock is located in close proximity to the connectors and produces clock pulses having a known rise time. Clock wiring is placed between the clock and the connectors, and module wiring carries the clock pulses from the connectors to the memory. The wiring has an impedance and length such that the round trip delay time of clock pulses between the clock and the memory is less than the rise time of the clock pulses. The clock is preferably located between the two banks of connectors to reduce wiring length to a minimum and minimize coupled noise.

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. There are two parts to the solution of reducing data line capacitance to an acceptable system limit. The first part involves designing a memory module with in-line bus switches. The bus switches are placed between the module tabs (system) and random access memory devices and are either in a high impedance (off) or active state. When in the high impedance state, the effective loading of the module is that of the bit switch device. The second part of the solution is to embed logic into an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches.

Abstract: Low voltage DRAMs are used on higher voltage memory modules in a way that requires no modification of the DRAMs. "Bus switch" technology and compact low voltage regulators are used at the module level. The low voltage regulator provides a lowered, regulated voltage to DRAMs. The bus switches are used at the inputs and outputs of the DRAMs and effectively protect the DRAM circuitry from voltage swings that could otherwise be damaging.

Abstract: Multiple synchronous dynamic random access memories (SDRAMs) are packaged in a single or a dual in-line memory module to have similar physical and architectural characteristics of dynamic random access memories (DRAMs) packaged in single/dual in-line memory modules. A 168 pin SDRAM DIMM family is presented which requires no modification of existing connector, planar or memory controller components. The 168 pin SDRAM DIMM family includes 64 bit non-parity, 72 bit parity, 72 bit ECC and 80 bit ECC memory organizations. Special placement and wiring of decoupling capacitors about the SDRAMs and the buffer chips contained within the module are also presented to reduce simultaneous switching noises during read and write operations. A special wiring scheme for the decoupling capacitors is employed to reduce wiring inductance.

Abstract: The present invention relates to a computer system and method of using the same in which add-on memory cards are provided which have error correction code logic on the card and logic to do partial writes of data words. The system has a central processing unit (CPU), and a BUS interconnecting the CPU and the add-on memory cards which are configured to write data and read data from the add-on memory. The system is further configured (either within the CPU or as a separate function) to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory.

Abstract: The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC).

Abstract: A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.

Abstract: A method and system for managing the utilization of power is provided. In a system having one or more devices, such as a memory subsystem having one or more banks of memory, the amount of power necessary for the operation of one or more of the devices is monitored and if possible, the power being supplied to one or more of the devices is reduced. A scoreboard located within a memory controller is used to retain the available power modes for each of the devices. When it is determined that it is desirable to reduce the power being supplied to a particular device, then the scoreboard is accessed in order to determine the lowest power level available for the device. Using this information, an amount of power commensurate with the lowest power level is applied to the device, thereby reducing the amount of power being applied to the device. In one aspect of the invention, a device is automatically placed in its lowest power level when it has not been accessed for a preselected amount of time.

Abstract: A computer system is provided which includes a CPU having a memory controller interconnecting the CPU to a bus. The bus has card receptacles having pin receiving sockets electrically connected to the bus to receive the pins of memory cards. The memory controller is connected to logic which will identify the type of memory card which is inserted in the pin sockets. From this identification combinational logic is provided that, in response to the identification of the type of card, will direct the appropriate signals from the memory controller to the appropriate sockets depending upon which type of card is plugged into the socket. In this way, a given socket configuration can accept different types of memory cards having different pin signal configurations without physical modification of the sockets.