Patents by Inventor Mark Waller
Mark Waller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8707239Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.Type: GrantFiled: December 11, 2012Date of Patent: April 22, 2014Assignee: Pulsic LimitedInventor: Mark Waller
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Patent number: 8490036Abstract: A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern.Type: GrantFiled: January 18, 2010Date of Patent: July 16, 2013Assignee: Pulsic LimitedInventor: Mark Waller
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Patent number: 8479141Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: January 17, 2012Date of Patent: July 2, 2013Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 8479139Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.Type: GrantFiled: July 9, 2010Date of Patent: July 2, 2013Assignee: Pulsic LimitedInventors: Graham Baldsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Patent number: 8332805Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: July 11, 2011Date of Patent: December 11, 2012Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
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Patent number: 8332799Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.Type: GrantFiled: July 19, 2011Date of Patent: December 11, 2012Assignee: Pulsic LimitedInventor: Mark Waller
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Publication number: 20120110539Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Applicant: PULSIC LIMITEDInventors: Jeremy Birch, Mark Waller, Graham Balsdon
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Patent number: 8171447Abstract: A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.Type: GrantFiled: March 20, 2009Date of Patent: May 1, 2012Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Patent number: 8099700Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: August 14, 2007Date of Patent: January 17, 2012Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 8095903Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.Type: GrantFiled: October 31, 2006Date of Patent: January 10, 2012Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Graham Balsdon
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Publication number: 20110276937Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: PULSIC LIMITEDInventor: Mark Waller
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Patent number: 8010928Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: March 14, 2008Date of Patent: August 30, 2011Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
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Patent number: 7984411Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.Type: GrantFiled: September 1, 2009Date of Patent: July 19, 2011Assignee: Pulsic LimitedInventor: Mark Waller
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Patent number: 7823113Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: September 11, 2006Date of Patent: October 26, 2010Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 7802208Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: August 14, 2007Date of Patent: September 21, 2010Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 7784010Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.Type: GrantFiled: June 1, 2004Date of Patent: August 24, 2010Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Publication number: 20100122227Abstract: A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern.Type: ApplicationFiled: January 18, 2010Publication date: May 13, 2010Applicant: PULSIC LIMITEDInventor: Mark Waller
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Patent number: 7657852Abstract: A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern.Type: GrantFiled: January 25, 2006Date of Patent: February 2, 2010Assignee: Pulsic LimitedInventor: Mark Waller
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Publication number: 20090327990Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.Type: ApplicationFiled: September 1, 2009Publication date: December 31, 2009Applicant: PULSIC LIMITEDInventor: Mark Waller
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Patent number: 7603644Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.Type: GrantFiled: June 22, 2006Date of Patent: October 13, 2009Assignee: Pulsic LimitedInventor: Mark Waller