Abstract: A flip-flop includes an input stage to receive a data signal and an output stage to provide an output signal. A clock input is directly connected to a transmission gate of the output stage and coupled by way of a delay circuit to a transmission gate of the input stage. A first latch is coupled between the transmission gate of the input stage and the output stage.

Abstract: A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one embodiment of the circuit, an evaluation transistor is positioned between a precharge transistor and a dynamic logic block. The evaluation transistor separates a precharge node from the logic block during a precharge clock phase so that the logic block is not charged. A delay coupled to the precharge transistor allows the precharge transistor to remain activated during a portion of an evaluation clock phase to overcome any effects of charge-sharing between the precharge node and the dynamic logic block. Because the evaluation transistor separates the logic block from the precharge node, the precharge node can be charged independently of the number of inputs present in the dynamic logic block.

Abstract: A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one embodiment of the circuit, an evaluation transistor is positioned between a precharge transistor and a dynamic logic block. The evaluation transistor separates a precharge node from the logic block during a precharge clock phase so that the logic block is not charged. A delay coupled to the precharge transistor allows the precharge transistor to remain activated during a portion of an evaluation clock phase to overcome any effects of charge-sharing between the precharge node and the dynamic logic block. Because the evaluation transistor separates the logic block from the precharge node, the precharge node can be charged independently of the number of inputs present in the dynamic logic block.

Abstract: A gate array architecture adapted for serial multiplexer-based circuits. In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein. In another embodiment, a base cell contains a single serial multiplexer circuit divisible into varying-sized (size corresponding to the number of inputs) derivative serial multiplexer circuits. In either embodiment, the serial multiplexer circuits within the base cell may be formed from P- and N-channel transistors of varying size. The transistor sizes are chosen to optimize the efficiency of serial multiplexer-based circuits.

Abstract: A gate array architecture adapted for circuits containing transmission gates. In one embodiment, the gate array architecture contains a base row having at least four alternating P- and N-channel transistor rows. The transistor rows are positioned between a first voltage and a second voltage rail. In another embodiment, the rows adjacent the first and second voltage rails have larger transistors to facilitate connection of the transistors as inverters or buffers. The rows more remotely positioned from the first and second voltage rails have smaller transistor sizes to facilitate connection of the transistors as transmission gates. The gate array architecture is particularly efficient when used to create serial multiplexer-based circuits.