Patents by Inventor Marko Scrbak
Marko Scrbak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111676Abstract: A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Marko Scrbak, Gabriel H. Loh, Akhil Arunkumar
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Publication number: 20240111425Abstract: A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored across the multiple grains of the plurality of grains.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, Marko Scrbak
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Publication number: 20240111677Abstract: A method for performing prefetching operations is disclosed. The method includes storing a recorded access pattern indicating a set of accesses for a region; in response to an access within the region, fetching the recorded access pattern; and performing prefetching based on the access pattern.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Gabriel H. Loh, Marko Scrbak, Akhil Arunkumar, John Kalamatianos
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Patent number: 11914517Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.Type: GrantFiled: November 11, 2020Date of Patent: February 27, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
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Patent number: 11847062Abstract: In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.Type: GrantFiled: December 16, 2021Date of Patent: December 19, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Tarun Nakra, Jay Fleischman, Gautam Tarasingh Hazari, Akhil Arunkumar, William L. Walker, Gabriel H. Loh, John Kalamatianos, Marko Scrbak
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Publication number: 20230359556Abstract: An electronic device includes a processor and a memory separate from the processor. The memory includes memory circuitry including a plurality of locations and processor in memory circuitry. In some implementations, some or all of the locations are used for storing cache blocks for a cache memory and the processor in memory circuitry performs operations for handling cache blocks in the memory circuitry. In some implementations, some or all of the locations are used for storing data for a memory and the processor in memory circuitry performs operations for handling data in the memory circuitry.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Jagadish B. Kotra, Marko Scrbak
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Patent number: 11762777Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.Type: GrantFiled: March 31, 2021Date of Patent: September 19, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, Marko Scrbak, Matthew Raymond Poremba
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Patent number: 11726783Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.Type: GrantFiled: April 23, 2020Date of Patent: August 15, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Marko Scrbak, Mahzabeen Islam, John Kalamatianos, Jagadish B. Kotra
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Publication number: 20230195643Abstract: In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Tarun Nakra, Jay Fleischman, Gautam Tarasingh Hazari, Akhil Arunkumar, William L. Walker, Gabriel H. Loh, John Kalamatianos, Marko Scrbak
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Patent number: 11681620Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.Type: GrantFiled: July 23, 2021Date of Patent: June 20, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Marko Scrbak, Jagadish Kotra
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Publication number: 20230022320Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.Type: ApplicationFiled: July 23, 2021Publication date: January 26, 2023Inventors: Marko Scrbak, Jagadish Kotra
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Publication number: 20220318151Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, Marko Scrbak, Matthew Raymond Poremba
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Publication number: 20220206946Abstract: Method and apparatus monitor eviction conflicts among cache directory entries in a cache directory and produce cache directory victim entry information for a memory manager. In some examples, the memory manager reduces future cache directory conflicts by changing a page level physical address assignment for a page of memory based on the produced cache directory victim entry information. In some examples, a scalable data fabric includes hardware control logic that performs the monitoring of the eviction conflicts among cache directory entries in the cache directory and produces the cache directory victim entry information.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Brandon K. Potter, Marko Scrbak, Sergey Blagodurov, Kishore Punniyamurthy, Nathaniel Morris
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Publication number: 20220100668Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.Type: ApplicationFiled: November 11, 2020Publication date: March 31, 2022Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
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Publication number: 20220027291Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Inventors: SERGEY BLAGODUROV, JOHNATHAN ALSOP, JAGADISH B. KOTRA, MARKO SCRBAK, GANESH DASIKA
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Publication number: 20210334098Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.Type: ApplicationFiled: April 23, 2020Publication date: October 28, 2021Inventors: Marko Scrbak, Mahzabeen Islam, John Kalamatianos, Jagadish B. Kotra