Abstract: A power supply particularly suitable for high-speed optical data transmission employs readily available components to achieve desired voltage tolerances. More specifically, a voltage signal supplied to a load is converted into a digital signal and provided to a processor that derives a digital correction signal from the digital signal. The digital correction signal is then converted to an analog correction signal and is used by a feedback control circuit in the power supply to regulate the output voltage.

Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: A power supply particularly suitable for high-speed optical data transmission employs readily available components to achieve desired voltage tolerances. More specifically, a voltage signal supplied to a load is converted into a digital signal and provided to a processor that derives a digital correction signal from the digital signal. The digital correction signal is then converted to an analog correction signal and is used by a feedback control circuit in the power supply to regulate the output voltage.

Abstract: The invention relates to an apparatus (1) for protection of electronic circuits with a decentralized power supply (PS1, PS2). One object of the invention is to avoid damage to other loads (PN1, PN2) which are still intact when a short circuit occurs in one load (PN1, PN2) in the circuit. The apparatus (1) comprises a number of loads (PN1, PN2) which are supplied in a decentralized manner. One monitoring device (PSUP1, PSUP2) in each case monitors a respective one of the load supply voltages (P1, P2) and ensures primary-side fault disconnection of all the power supplies (PS1, PS2) if a threshold value is undershot.

Abstract: The invention relates to an apparatus (1) for protection of electronic circuits with a decentralized power supply (PS1, PS2). One object of the invention is to avoid damage to other loads (PN1, PN2) which are still intact when a short circuit occurs in one load (PN1, PN2) in the circuit. The apparatus (1) comprises a number of loads (PN1, PN2) which are supplied in a decentralized manner. One monitoring device (PSUP1, PSUP2) in each case monitors a respective one of the load supply voltages (P1, P2) and ensures primary-side fault disconnection of all the power supplies (PS1, PS2) if a threshold value is undershot.

Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: A device and method for ensuring parallel data transmission and reception based on a high speed transmission rate between an electrical system (1) and an optical network (2) adapted for optical data transmission, wherein a plurality of logical channels (TXDATA, RXDATA) with the data to be transmitted embedded therein is synchronously transmitted from the electrical system (1) to the optical network (2) together with an additional control channel (TXPAR) comprising information usable for detecting a transmission error by a respective adapted receiving means of the optical network, and wherein a clock rate is ensured having the half rate in relation to the transmission rate of a respective logical channel (TXDATA, RXDATA).

Abstract: A phase detector including a voltage controlled oscillator generating a voltage controlled oscillator output, and a first logic state device for receiving said voltage controlled oscillator output as an input. The phase detector also includes a reset device, for generating a reset signal to reset the first logic state device such that the output control signal of the first logic state device reaches a low level in response to a first edge of the reset signal.

Abstract: The present invention relates generally to the field phase detectors and particularly to a phase detector being formed by a flip-flop.

Abstract: The invention relates to a transmission system comprising a phase-locked loop (12) which includes a phase comparator (15) for comparing an oscillator signal with a reference signal and for generating a comparison signal, and an oscillator which is provided for receiving a control signal derived from the comparison signal. The oscillator arranged as a ring oscillator (14) comprises at least one delay element (27 to 31) included in a closed circuit. At least one delay element (27 to 30) has at least two different adjustable delay times. A controller (19) is provided for setting the delay times of at least one delay element (27 to 30) in dependence on the comparison signal.