Abstract: A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Abstract: A method, apparatus and system testing a plurality of semiconductor chips in a distributed memory buffer system is provided. Embodiments of the present invention recognize improvements to testing signals through the chip substrate and motherboard. This invention overloads the shared broadcast bus by using it for test purposes rather than its normal mainline function. One of the main components of this invention is the A/C chip. In test mode, the AC chip converts JTAG commands into an internal test format and sends test data over the shared broadcast bus. Each data chip determines whether the scan data is for itself or if it should ignore it. The corresponding data chip then processes the data, and if necessary sends return data back to the address and command chip, where it is converted back into JTAG format and can be seen by the tester.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Abstract: A method, apparatus and system testing a plurality of semiconductor chips in a distributed memory buffer system is provided. Embodiments of the present invention recognize improvements to testing signals through the chip substrate and motherboard. This invention overloads the shared broadcast bus by using it for test purposes rather than its normal mainline function. One of the main components of this invention is the A/C chip. In test mode, the AC chip converts JTAG commands into an internal test format and sends test data over the shared broadcast bus. Each data chip determines whether the scan data is for itself or if it should ignore it. The corresponding data chip then processes the data, and if necessary sends return data back to the address and command chip, where it is converted back into JTAG format and can be seen by the tester.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.

Abstract: The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.