Abstract: A linear actuator includes a piston, a transmitter, and a receiver. The piston is configured to linearly extend and retract (such as within a cover tube). The transmitter is configured to generate a transmit electromagnetic waveform and direct the transmit electromagnetic waveform along a length of the piston. The receiver is configured to receive a return electromagnetic waveform that includes the transmit electromagnetic waveform after travelling to an extended end of the piston and returning to the receiver and determine a position of the piston based on a phase difference between the transmit electromagnetic waveform and the return electromagnetic waveform.

Abstract: A linear actuator includes a piston, a transmitter, and a receiver. The piston is configured to linearly extend and retract (such as within a cover tube). The transmitter is configured to generate a transmit electromagnetic waveform and direct the transmit electromagnetic waveform along a length of the piston. The receiver is configured to receive a return electromagnetic waveform that includes the transmit electromagnetic waveform after travelling to an extended end of the piston and returning to the receiver and determine a position of the piston based on a phase difference between the transmit electromagnetic waveform and the return electromagnetic waveform.

Abstract: A linear actuator includes a piston, a transmitter, and a receiver. The piston is configured to linearly extend and retract (such as within a cover tube). The transmitter is configured to generate a transmit electromagnetic waveform and direct the transmit electromagnetic waveform along a length of the piston. The receiver is configured to receive a return electromagnetic waveform that includes the transmit electromagnetic waveform after travelling to an extended end of the piston and returning to the receiver and determine a position of the piston based on a phase difference between the transmit electromagnetic waveform and the return electromagnetic waveform.

Abstract: A linear actuator includes a piston, a transmitter, and a receiver. The piston is configured to linearly extend and retract (such as within a cover tube). The transmitter is configured to generate a transmit electromagnetic waveform and direct the transmit electromagnetic waveform along a length of the piston. The receiver is configured to receive a return electromagnetic waveform that includes the transmit electromagnetic waveform after travelling to an extended end of the piston and returning to the receiver and determine a position of the piston based on a phase difference between the transmit electromagnetic waveform and the return electromagnetic waveform.

Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Abstract: An input bus termination (IBT) system for an integrated circuit that includes a termination switch coupled to a plurality of input lines of an integrated circuit, each of the plurality of input lines coupled to a common node of the termination switch through a resistor, wherein the termination switch is to generate a termination voltage at the common node based on the composite potential generated by the plurality of input lines at the common node when an input signal is received across the plurality of input lines.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: A phase locked loop (PLL) is provided. The PLL includes a control stage comprising N storage elements each having an output coupled to the output of the control stage. The N storage elements being coupled in a chain, and each storage element being configurable in an analog mode, where a stored signal at the storage node of the storage element is changed continuously in response to the output signal of a charge pump. Each storage element is configurable in a digital mode in which the stored value is one value out of a predetermined set of values, and the storage element can assume the analog mode if a preceding storage element and a subsequent storage element are in the digital mode and have different values of the stored signal.

Abstract: An integrated phase adjusting circuit (12) for the generation of a clock output signal (CLKout) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is proposed. The circuit has an interpolator unit (30) which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, and is controlled externally by a control signal (PHfine) to execute a phase step if the phase of the clock signal is to be shifted. The circuit (12) comprises a synchronization unit (40) which synchronizes the phase step with the clock output signal generated by the circuit.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A buffer chain driver has two similar signal paths formed by series-connected buffer cells, each comprising two series connected inverter stages in each signal path. The output of the first inverter stage in each signal path is coupled to the output of the last inverter stage in the other signal path. Cross-coupling between the two signal paths results in an interpolation in the sense that each signal path has a 50% contribution to each of the complementary output signals, thereby compensating for any mismatch between the signal paths.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the phase locked loop circuit with a low loop gain and a wide frequency pulling range, a plurality of discrete capacitors is associated with the voltage controlled oscillator. A switch array selectively activates and deactivates each of the capacitors in the voltage controlled oscillator. Each number of currently activated capacitors determines one out of a plurality of partial ranges of frequencies through which the oscillator can be tuned by a variation of the control voltage in a range between predetermined upper and lower control voltage limits. A total frequency range through which the oscillator can be tuned is divided thus into a plurality of partial frequency ranges each defined by a different number of activated capacitors.

Abstract: An oscillator includes a first oscillator ring with a number of cascaded inverting delay stages and a second oscillator ring with a number of cascaded inverting delay stages. The ring oscillator also includes a number of inverter pairs which each consists of a first inverter and a second inverter, an input of the first inverter being connected with an output of the second inverter and an input of the second inverter being connected with an output of the first inverter. Each inverter pair connects a node of the first oscillator ring with a node of the second oscillator ring. Since phase noise in an oscillator is dominated by the ratio of the power in the edges of the oscillator signal versus the voltage noise that affects the delay of one oscillator stage, essentially all the consumed power is used for the switching process, implementing very steep edges of the oscillator signal.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A fractional-N divider for dividing a frequency f of an output signal by N, where N is a non-integer. The fractional-N divider includes an oscillator 209 adapted to provide K output signals I,I=I1, . . . , IK. Each output signal I has the same frequency f and period T. The output signals I are mutually phase shifted by T/K or a multiple of T/K. The fractional-N divider further comprises a multiplexer 211 adapted to select one signal from the K output signals I. The selected signal is phase shifted by M*T/K in relation to a previously selected signal, where M is an integer. Additionally, the fractional-N divider comprises a counter 206 adapted to receive said selected signal. The counter 206 is adapted to count a predetermined number X of periods of the selected signal, whereupon the counter 206 outputs a counter signal 230. The counter 206 is connected to a control input of the multiplexer 211.

Abstract: An integrated phase adjusting circuit (12) for the generation of a clock output signal (CLKout) with a phase intermediate the phases of first and second input signals of equal frequency with a fixed phase shift between said first and second signals is proposed. The circuit has an interpolator unit (30) which determines the phase of the clock signal relative to either one of the first input signal and the second input signal, and is controlled externally by a control signal (PHfine) to execute a phase step if the phase of the clock signal is to be shifted. The circuit (12) comprises a synchronization unit (40) which synchronizes the phase step with the clock output signal generated by the circuit.

Abstract: A circuit generating an output phase signal with an optionally variable phase shift relative to a reference phase. It includes an oscillator (10) outputting phase signals at n outputs, each of which differs in phase by ?=360°/n. These phase signals are applied selectively via multiplexers to a phase interpolator, at the output of which the signal changed in phase relative to a reference phase. The output phase signal is generated in a charging circuit in which a capacitor can be varied by signaling current sources ON/OFF with the aid of phase switches in accordance with the phasing to be produced for the output signal. To avoid jitter in the transition from one phase to another separating switches are inserted in the connection between the current sources and the charging circuit, these separating switches being controlled so that they are never open at the same time.

Abstract: An output driver circuit includes an input stage to which an input voltage is applied, and an output stage to which an output voltage is applied, input stage and output stage being connected by at least one supply voltage terminal and/or at least one ground terminal to which at least one parasitic inductance is applied, and the input stage and output stage being configured so that when the difference amount between a potential as a function of the input voltage and a potential as a function of the supply voltage and/or ground voltage exceeds a predefined first threshold value or drops below a predefined second threshold value a flow of current is activated or deactivated respectively in the output stage via the supply voltage terminal(s) and/or the ground terminal(s) which also flows via the parasitic inductance(s).