Patents by Inventor Markus Dinkel
Markus Dinkel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10699987Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.Type: GrantFiled: April 16, 2018Date of Patent: June 30, 2020Assignee: tInfineon Technologies Austria AGInventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
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Publication number: 20200144150Abstract: A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
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Publication number: 20200135619Abstract: In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.Type: ApplicationFiled: October 30, 2019Publication date: April 30, 2020Inventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
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Patent number: 10566260Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.Type: GrantFiled: September 7, 2018Date of Patent: February 18, 2020Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
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Publication number: 20190080980Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.Type: ApplicationFiled: September 7, 2018Publication date: March 14, 2019Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
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Patent number: 10168391Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.Type: GrantFiled: February 22, 2016Date of Patent: January 1, 2019Assignee: Infineon Technologies AGInventors: Giuliano Angelo Babulano, Jens Oetjen, Liu Chen, Toni Salminen, Stefan Mieslinger, Markus Dinkel, Martin Gruber, Franz Jost, Thorsten Meyer, Rainer Schaller
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Publication number: 20180301398Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.Type: ApplicationFiled: April 16, 2018Publication date: October 18, 2018Inventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
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Patent number: 9935027Abstract: An electronic device having a substrate including a metal layer, an electrically insulating layer disposed above the substrate, a semiconductor module disposed above the electrically insulating layer and a lamination layer disposed above the electrically insulating layer. The lamination layer at least partially embeds the semiconductor module.Type: GrantFiled: April 13, 2016Date of Patent: April 3, 2018Assignee: Infineon Technologies AGInventor: Markus Dinkel
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Patent number: 9922904Abstract: A semiconductor device includes a planar first lead frame including a die pad, a semiconductor chip coupled to the die pad, and a second lead frame coupled to the first lead frame. The second lead frame includes leads arranged such that the die pad is downset with respect to the leads.Type: GrantFiled: May 26, 2015Date of Patent: March 20, 2018Assignee: Infineon Technologies AGInventor: Markus Dinkel
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Patent number: 9881853Abstract: A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.Type: GrantFiled: April 4, 2016Date of Patent: January 30, 2018Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Markus Dinkel
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Publication number: 20170287820Abstract: A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.Type: ApplicationFiled: April 4, 2016Publication date: October 5, 2017Inventors: Dirk Ahlers, Markus Dinkel
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Publication number: 20170271246Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.Type: ApplicationFiled: March 21, 2016Publication date: September 21, 2017Applicant: Infineon Technologies AGInventors: Stefan Macheiner, Markus Dinkel
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Patent number: 9681558Abstract: A integrated power module with integrated power electronic circuitry and logic circuitry includes an embedded power semiconductor module including one or more power semiconductor dies embedded in a dielectric material, a multi-layer logic printed circuit board with one or more logic dies mounted to a surface of the logic printed circuit board, and a flexible connection integrally formed between the embedded power semiconductor module and the logic printed circuit board. The flexible connection mechanically connects the embedded power semiconductor module to the logic printed circuit board and provides an electrical pathway between the embedded power semiconductor module and the logic printed circuit board. A method of manufacturing the integrated power module is also provided.Type: GrantFiled: August 12, 2014Date of Patent: June 13, 2017Assignee: Infineon Technologies AGInventors: Liu Chen, Markus Dinkel, Toni Salminen
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Patent number: 9570433Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 ?m along the edges of the semiconductor substrate beginning at the corner.Type: GrantFiled: September 21, 2015Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Markus Zundel, Vanessa Capodieci, Markus Dinkel, Uwe Schmalzbauer
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Patent number: 9564423Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.Type: GrantFiled: June 23, 2015Date of Patent: February 7, 2017Assignee: Infineon Technologies AGInventors: Liu Chen, Toni Salminen, Stefan Mieslinger, Giuliano Angelo Babulano, Jens Oetjen, Markus Dinkel, Franz Jost
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Patent number: 9564578Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.Type: GrantFiled: November 20, 2015Date of Patent: February 7, 2017Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Martin Gruber, Rainer Markus Schaller, Franz Jost, Stefan Mieslinger, Liu Chen, Toni Salminen, Giuliano Angelo Babulano, Jens Oetjen, Markus Dinkel
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Publication number: 20160377689Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.Type: ApplicationFiled: February 22, 2016Publication date: December 29, 2016Inventors: Giuliano Angelo Babulano, Jens Oetjen, Liu Chen, Toni Salminen, Stefan Mieslinger, Markus Dinkel, Martin Gruber, Franz Jost, Thorsten Meyer, Rainer Schaller
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Publication number: 20160379966Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.Type: ApplicationFiled: June 23, 2015Publication date: December 29, 2016Inventors: Liu Chen, Toni Salminen, Stefan Mieslinger, Giuliano Angelo Babulano, Jens Oetjen, Markus Dinkel, Franz Jost
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Publication number: 20160380181Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.Type: ApplicationFiled: November 20, 2015Publication date: December 29, 2016Inventors: Thorsten Meyer, Martin Gruber, Rainer Markus Schaller, Franz Jost, Stefan Mieslinger, Liu Chen, Toni Salminen, Giuliano Angelo Babulano, Jens Oetjen, Markus Dinkel
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Publication number: 20160351475Abstract: A semiconductor device includes a planar first lead frame including a die pad, a semiconductor chip coupled to the die pad, and a second lead frame coupled to the first lead frame. The second lead frame includes leads arranged such that the die pad is downset with respect to the leads.Type: ApplicationFiled: May 26, 2015Publication date: December 1, 2016Applicant: INFINEON TECHNOLOGIES AGInventor: Markus Dinkel