Abstract: A cryptographic hardware module has an arithmetic unit, a memory storing at least one first key, a logic and a cryptographic device. The hardware module loads at least one second encrypted key into the hardware module and decrypts the at least one second encrypted key via the cryptographic device using the at least one first key.

Abstract: A communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module having a communication protocol unit, which is connected to the serial bus, for converting between data packages and messages, which are respectively made up of a plurality of data words, a message relaying unit for relaying messages between at least one message memory and the communication protocol unit, as well as buffer memories, a plurality of interface units, which are respectively connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory, which stores a message temporarily, a transmission of data words via a plurality of system buses and their associated interface units from and to the buffer memories of the interface units taking place simultaneously, without delay.

Abstract: A multiprocessor gateway for multiple serial buses includes: multiple communication modules that are each provided for connection of one serial bus; multiple processors for processing data that are transferred in word-based fashion, via an internal system bus appurtenant to the respective processor, between the processor and the communication modules, the internal system buses of the multiprocessor gateway being connected to the communication modules, which have a respective appurtenant interface unit for each system bus, each processor exchanging data, via its appurtenant system bus and the interface unit, appurtenant to the system bus, of a communication module, with the serial bus connected to the communication module, independently of the other processors and without waiting time.

Abstract: A subscriber node of a communication system, a communication system and a method for transmitting a message in the communication system. The message is transmitted from a first subscriber node of the communication system via a data bus of the communication system to a second subscriber node of the communication system. An application program of the first subscriber node files the message, that is to be sent, in a message memory, from where it is retrieved by a communication controller, upon a sending command of the application program, and is transmitted via the data bus.

Abstract: A method for operating a security device includes a microcontroller, a protected memory area, in which at least one item of protection-worthy information is stored, and a unit, the microcontroller being connected to the protected memory area via the unit, the at least one item of protection-worthy information being accessed by the microcontroller via the unit when the method is carried out.

Abstract: A method and a filter system for filtering messages which are received, via a serial data bus of a communications network, in a communication module of a user connected to the data bus. To allow particularly simple and efficient filtering of incoming messages, even when there is a large number of filtering criteria, it is proposed that the filter system includes a list in which multiple identifier pairs are stored which define a range delimited in each case by a first identifier and a second identifier. The identifier for an incoming message is compared at least to selected identifier pairs from the list, and a query is made concerning whether the identifier for the incoming message is greater than, or greater than or equal to, the selected first identifier, and is less than, or less than or equal to, the selected second identifier.

Abstract: A gateway is provided for automatically routing messages between buses, the gateway being connected to multiple communication components for temporarily storing and transmitting messages via these buses, and having a gateway control unit which is connected to the communication components via a system bus for the exchange of messages, and which receives notification from each communication component of the occurrence therein of a message to be routed as an external event. The gateway control unit has a vector memory which includes a first memory region for storing communication component vectors, a communication component vector being provided for each message group of a communication component, and the vector indicating the point in time of the next expected internal event for a message that is temporarily stored in the communication component, and indicating a vector jump address to a message vector which is stored in a second memory region of the vector memory.

Abstract: A user interface between a FlexRay communications module which is connected to a FlexRay communications link over which messages are transmitted and which includes a message memory for buffer storing messages from the FlexRay communications link or for the FlexRay communications link, and a microcontroller which is assigned to the FlexRay communications module and which includes a microprocessor and a direct memory access (DMA) controller for exchanging data with the message memory. In order for the DMA controller of the microcontroller to be connected more effectively to the FlexRay communications module, the user interface has a state machine, which, once configured by the microprocessor of the microcontroller, independently coordinates and controls a data transmission between the message memory of the FlexRay communications module and the DMA controller.

Abstract: A communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module having a communication protocol unit, which is connected to the serial bus, for converting between data packages and messages, which are respectively made up of a plurality of data words, a message relaying unit for relaying messages between at least one message memory and the communication protocol unit, as well as buffer memories, a plurality of interface units, which are respectively connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory, which stores a message temporarily, a transmission of data words via a plurality of system buses and their associated interface units from and to the buffer memories of the interface units taking place simultaneously, without delay.

Abstract: A subscriber of a communication system includes a microprocessor, at least two communication controllers and a peripheral bus. The microprocessor is connected to the communication controllers via the peripheral bus and is also connected via the communication controllers respectively to a communication link of the communication system, via which messages are transmitted. In order to optimize the gateway functionality within the subscriber, a provision is made that at least one of the communication controllers has an active interface via which the communication controller is connected to the peripheral bus and has a logic circuit for independently implementing a gateway functionality.

Abstract: A multiprocessor gateway for multiple serial buses includes: multiple communication modules that are each provided for connection of one serial bus; multiple processors for processing data that are transferred in word-based fashion, via an internal system bus appurtenant to the respective processor, between the processor and the communication modules, the internal system buses of the multiprocessor gateway being connected to the communication modules, which have a respective appurtenant interface unit for each system bus, each processor exchanging data, via its appurtenant system bus and the interface unit, appurtenant to the system bus, of a communication module, with the serial bus connected to the communication module, independently of the other processors and without waiting time.

Abstract: A gateway for data transfer between serial buses, including multiple communication modules that are each provided for connection of one serial bus, and that carry out a conversion between data packets and data words, a bus master that, via an internal control bus, controls a word-based transfer of data via an internal data bus between two communication modules, the bus master applying a source address via a source address bus to an internally transmitting first communication module, and a destination address via a separate destination address bus to an internally receiving second communication module, data received in data packets by the first communication module via a first serial bus connected thereto being transferred from the first communication module directly without buffering, in word-based fashion in one or more data words, via the internal data bus to the second communication module, which delivers these transferred data, in data packets, via a second serial bus connected to the second communication

Abstract: A gateway is provided for automatically routing messages between buses, the gateway being connected to multiple communication components for temporarily storing and transmitting messages via these buses, and having a gateway control unit which is connected to the communication components via a system bus for the exchange of messages, and which receives notification from each communication component of the occurrence therein of a message to be routed as an external event. The gateway control unit has a vector memory which includes a first memory region for storing communication component vectors, a communication component vector being provided for each message group of a communication component, and the vector indicating the point in time of the next expected internal event for a message that is temporarily stored in the communication component, and indicating a vector jump address to a message vector which is stored in a second memory region of the vector memory.

Abstract: A FlexRay communications module for coupling a FlexRay communications link, over which messages are transmitted, to a participant, which is assigned via a participant interface to the FlexRay communications module. To provide a FlexRay communications module which will optimally support the communication processes in a FlexRay network, the FlexRay communications module includes a configuration for storing messages transmitted or to be transmitted between the participant and the FlexRay communications link, and a state machine which, to control the transmission of the messages, specifies and/or invokes sequences relating to information for storing messages in the configuration, for invoking messages from the configuration, and for transmitting the messages.

Abstract: FlexRay communication controller for connecting FlexRay communication lines to a FlexRay network member assigned to the FlexRay communication controller, whereby said FlexRay communication controller encloses some parts as there are at least a message handler, a message memory, a first buffer memory structure for connecting said message memory to said FlexRay network member and a second buffer memory structure for connecting said message memory to said FlexRay communication lines, whereby all the parts are functioning together to connect said FlexRay communication lines to said FlexRay network member and said FlexRay communication controller is constructed in such a way that said functioning is controlled by the contents of a variety of registers located onto said FlexRay communication controller.

Abstract: A method for controlling access to data of a message memory, and a message handler of a communications module having a message memory, in which data are input or output in response to an access; the message memory being connected to a first buffer configuration and a second buffer configuration, and the data being accessed via the first or the second buffer configuration; in the message handler, at least one first finite state machine being provided which controls the access to the message memory via the first buffer configuration, and at least one second finite state machine being provided which controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; and a third finite state machine being provided which assigns access to the message memory to the at least one first and the second finite state machine as a function of their access requests.