Patents by Inventor Markus Waidelich

Markus Waidelich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6874051
    Abstract: A system carrier for freely programmable blocks that are connected to one another by buses, of a carrier body, at least three identically configured connectors disposed on the carrier body and being configured to receive in each case one module with a freely programmable block, the module being couplable to the connector and its position changable, and three groups of buses arranged to fixedly connect the connectors to one another.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: March 29, 2005
    Assignee: IsarTec GmbH
    Inventors: Helmuth Gesch, Markus Waidelich
  • Publication number: 20030005198
    Abstract: The invention concern a system carrier for freely programmable blocks (gate arrays) that are connected to one another by means of buses. At least three identically configured connectors (24) for receiving a module (12) with a freely programmable block (18) are disposed on the system carrier (10). The module can be coupled to the connector (24) and its position changed, whereby the connectors (24) are fixedly connected to one another by means of three groups of buses (28, 30, 32).
    Type: Application
    Filed: August 15, 2002
    Publication date: January 2, 2003
    Inventors: Helmuth Gesch, Markus Waidelich
  • Patent number: 6492824
    Abstract: The invention relates to an adapter base for receiving electronic test objects (DLTT) comprising an outer group (array) of contact pins (26) that pass through the base from the upper side to the lower side, as well as an inner matrix (38) that consists of contacts (36) that protrude only on the lower side corresponding to an area (28) on the upper side which presents no contacts. Each contact pin (26) is connected to a series connection (30) embodied in the adaptor (24) and constituted by a switching transistor (32), as well as at least one capacitor (34) that via a control signal can be connected and disconnected by means of the gate (G) of the switching transistor (32), the gate being connected to a corresponding contact (36) on the lower side.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: December 10, 2002
    Inventors: Helmuth Gesch, Markus Waidelich
  • Patent number: 5524174
    Abstract: An apparatus for inference formation and defuzzification has an arithmetic unit, a memory/register unit, and a controller, wherein crisp output signals can be formed from weighting factors and dimensional scaling numbers dependent on control signals with a weighting factor being provided for each linguistic value of the output variables, the dimensional numbers characterizing the membership functions of the linguistic values of the output variables. The apparatus exhibits high processing speed and requires only low storage space, particularly given definitions of the crisp output signal of greater than or equal to eight bits.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: June 4, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Herbert Eichfeld, Markus Waidelich