Patents by Inventor Marlin Wayne Frederick
Marlin Wayne Frederick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11836432Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.Type: GrantFiled: November 6, 2020Date of Patent: December 5, 2023Assignee: Arm LimitedInventors: Sharath Koodali Edathil, Marlin Wayne Frederick, Jr.
-
Patent number: 11380618Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.Type: GrantFiled: February 2, 2018Date of Patent: July 5, 2022Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
-
Publication number: 20220188496Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.Type: ApplicationFiled: March 2, 2022Publication date: June 16, 2022Inventors: Sharath Koodali Edathil, Marlin Wayne Frederick, JR.
-
Publication number: 20220147679Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.Type: ApplicationFiled: November 6, 2020Publication date: May 12, 2022Inventors: Sharath Koodali Edathil, Marlin Wayne Frederick, JR.
-
Patent number: 11288432Abstract: Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.Type: GrantFiled: October 3, 2020Date of Patent: March 29, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Gus Yeung, Marlin Wayne Frederick, Jr., Sriram Thyagarajan
-
Patent number: 11152139Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.Type: GrantFiled: July 16, 2018Date of Patent: October 19, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk, Sharrone Rena Smith
-
Patent number: 11068639Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.Type: GrantFiled: October 19, 2018Date of Patent: July 20, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong
-
Publication number: 20210167013Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.Type: ApplicationFiled: February 13, 2021Publication date: June 3, 2021Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk
-
Patent number: 11011222Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.Type: GrantFiled: March 6, 2019Date of Patent: May 18, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Ronald Paxton Preston, Andy Wangkun Chen, Yew Keong Chong
-
Patent number: 10923425Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.Type: GrantFiled: January 17, 2018Date of Patent: February 16, 2021Assignee: Arm LimitedInventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
-
Publication number: 20210019463Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: ApplicationFiled: October 3, 2020Publication date: January 21, 2021Inventors: Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Gus Yeung, Marlin Wayne Frederick, JR., Sriram Thyagarajan
-
Patent number: 10796053Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: GrantFiled: September 24, 2018Date of Patent: October 6, 2020Assignee: Arm LimitedInventors: Paul de Dood, Marlin Wayne Frederick, Jr., Jerry Chaoyuan Wang, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Daniel J. Albers, David William Granda
-
Publication number: 20200286548Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.Type: ApplicationFiled: March 6, 2019Publication date: September 10, 2020Inventors: Marlin Wayne Frederick, JR., Ronald Paxton Preston, Andy Wangkun Chen, Yew Keong Chong
-
Publication number: 20200125693Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Marlin Wayne Frederick, Jr., Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong
-
Publication number: 20200020464Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.Type: ApplicationFiled: July 16, 2018Publication date: January 16, 2020Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk, Sharrone Rena Smith
-
Patent number: 10417371Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.Type: GrantFiled: January 27, 2017Date of Patent: September 17, 2019Assignee: ARM LimitedInventors: Karen Lee Delk, Marlin Wayne Frederick, Jr., Ravindra Narayana Rao
-
Publication number: 20190244900Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.Type: ApplicationFiled: February 2, 2018Publication date: August 8, 2019Inventors: Marlin Wayne Frederick, JR., Karen Lee Delk
-
Patent number: 10210303Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.Type: GrantFiled: January 27, 2017Date of Patent: February 19, 2019Assignee: ARM LimitedInventors: Ravindra Narayana Rao, Marlin Wayne Frederick, Jr., Karen Lee Delk, Stefan Charles Creaser
-
Patent number: 10204894Abstract: An integrated circuit layout includes a routing layout of routing conductors and routing connection vias formed prior to a power grid connection which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.Type: GrantFiled: September 8, 2016Date of Patent: February 12, 2019Assignee: ARM LimitedInventor: Marlin Wayne Frederick, Jr.
-
Publication number: 20190026417Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.Type: ApplicationFiled: September 24, 2018Publication date: January 24, 2019Inventors: Paul de Dood, Marlin Wayne Frederick, JR., Jerry Chaoyuan Wang, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Daniel J. Albers, David William Granda