Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

Abstract: The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.

Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.

Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

Abstract: The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.

Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.