Abstract: An attached storage media link has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a high speed, cost effective interface to a direct access storage device.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is characterized as having its own memory, by either at least one channel which is independent of and coupled to the multiple physical processing nodes or by at least one input/output (I/O) processor, again which is independent of and coupled to the multiple physical processing nodes. The at least one channel and/or the at least one I/O processor couple the multiple physical processing nodes to at least one shared input/output device. Sharing of the at least one channel and/or at least one I/O processor is practical by providing "indirect logical addressing" using logical address tables within the channel subsystem. The logical address tables associate an image identifier (Image.sub.-- ID) and processing node identifier (PN.sub.-- ID) concatenation with an indexed logical address for use in communicating I/O operation parameters across the at least one channel.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: Automatic machine methods and apparatus for determining which components of an I/O configuration are shared by other components of the configuration. The information can be obtained through the use of existing self-description facilities and unique identifiers. By noting which channel paths are used to obtain configuration-data records and examining the unique identifiers provided for each I/O items it can be determined which I/O devices are accessible through the same control unit, and which control units provide access to the same I/O device. Furthermore, by examining the unique identifiers provided, it can be determined which I/O subsystems and which control units or channel subsystems are accessible through the same dynamic switch and which dynamic switches provide access to the same I/O subsystem of channel subsystem.

Abstract: A method and system to eliminate service hardware previously provided with an adapter by providing a novel way to transfer its hardware service functions to a remote service hardware found elsewhere in a computer system, such as a mainframe. The transferred service controls include enabling the remote service hardware to control the updating of the adapter microcode; remotely control a recovery process for the adapter by remotely initializing its microcode, and remotely logging out and recovering from error conditions detected in the adapter; and remotely forcing a logout and recovery when the host OS detects a failure in the adapter. A standard I/O channel interface (optical or electronic) is provided between the adapter and an IOSS (Input Output Subsystem) of a computer system which has its own service processor element (SPE) used for servicing the computer system per se. The invention provides virtual service hardware for the adapter, but uses the SPE for its service hardware.

Abstract: An Internal I/O Facility (iIOF) having a general interface for executing I/O related applications in an Input/Ouput SubSystem (IOSS) of a computer system. IIOF applications are executed in the IOSS outside the scope of CPU applications executed under the operating system (OS) of the computer system. IIOF applications are allowed to use all facilities in the IOSS. An iIOF subchannel extension is provided for those subchannels which can execute an iIOF application. IIOF subchannel extensions contain interception control fields which determine if conventional processing for the subchannel by the IOSS is to be intercepted to execute an iIOF application. A front-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is taken from the IOSS work request queue. A back-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is to have status put on the IOSS interruption queue.