Abstract: A method for interfacing with an XML (Extensible Markup Language) parser generator to generate deserialization information interleaved with XML parsing and validation, including: providing an XML parser generator with information about the schema which the instance data conforms to; providing a data reporting application programming interface (API) and a generator module; providing one or more implementations of the data reporting API; providing the XML parser generator with a selected data reporting API implementation module; generating an XML parser to parse and validate instance documents conforming to the specified input schema and deserializing the instance documents into the desired deserialization format during the parse.

Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.

Abstract: A method for interfacing with an XML (Extensible Markup Language) parser generator to generate deserialization information interleaved with XML parsing and validation, including: providing an XML parser generator with information about the schema which the instance data conforms to; providing a data reporting application programming interface (API) and a generator module; providing one or more implementations of the data reporting API; providing the XML parser generator with a selected data reporting API implementation module; generating an XML parser to parse and validate instance documents conforming to the specified input schema and deserializing the instance documents into the desired deserialization format during the parse.

Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.

Abstract: A method for interfacing with an XML (Extensible Markup Language) parser generator to generate deserialization information interleaved with XML parsing and validation, including: providing an XML parser generator with information about the schema which the instance data conforms to; providing a data reporting application programming interface (API) and a generator module; providing one or more implementations of the data reporting API; providing the XML parser generator with a selected data reporting API implementation module; generating an XML parser to parse and validate instance documents conforming to the specified input schema and deserializing the instance documents into the desired deserialization format during the parse.

Abstract: A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.

Abstract: A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.