Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

Abstract: Wear levelling techniques based on use of a Galois field for the logical to physical translation of data addresses for a non-volatile memory, such as an MRAM-based memory, are presented. This not only provides a wear levelling technique to extend memory life, but also adds an additional layer of security to the stored memory data. More specifically, the following presents embodiments for secure wear levelling based on a Galois field having an order based on the size of the memory. To further improve security, a randomly generated rotation of the logically address based on the Galois field can also be used.

Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.

Abstract: A data storage device comprises a host interface and a storage control system coupled to the host interface. The storage control system is configured to perform a write process to write data to storage in response to one or more write operations received over the host interface from a host, determine a quality of written data produced by the write process; and in response to when the quality of the written data fails to satisfy one or more quality criteria, obtain data parity information to compensate for the quality of the written data and write the data parity information to storage.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.

Abstract: A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.

Abstract: A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.

Abstract: A data storage device comprises a host interface and a storage control system coupled to the host interface. The storage control system is configured to perform a write process to write data to storage in response to one or more write operations received over the host interface from a host, determine a quality of written data produced by the write process; and in response to when the quality of the written data fails to satisfy one or more quality criteria, obtain data parity information to compensate for the quality of the written data and write the data parity information to storage.

Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device is presented that performs a write process to store data on a storage medium of the data storage device responsive to one or more write operations received over a host interface. The data storage device monitors a quality of the write process and determines when the quality of the write process falls below a threshold quality. Responsive to the quality of the write process falling below the threshold quality, the data storage device indicates the quality of the write process to a data protection node for determination of data parity information that compensates for the quality of the write process, where the data parity information is provided by the data protection node for storage in a selected parity storage device.

Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device is presented that performs a write process to store data on a storage medium of the data storage device responsive to one or more write operations received over a host interface. The data storage device monitors a quality of the write process and determines when the quality of the write process falls below a threshold quality. Responsive to the quality of the write process falling below the threshold quality, the data storage device indicates the quality of the write process to a data protection node for determination of data parity information that compensates for the quality of the write process, where the data parity information is provided by the data protection node for storage in a selected parity storage device.

Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device is presented that performs a write process to store data on a storage medium of the data storage device responsive to one or more write operations received over a host interface. The data storage device monitors a quality of the write process and determines when the quality of the write process falls below a threshold quality. Responsive to the quality of the write process falling below the threshold quality, the data storage device indicates the quality of the write process to a data protection node that determines data parity information for the data to compensate for the quality of the write process. The data storage device receives the data parity information and stores the data parity information.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.

Abstract: Embodiments of the present invention provide techniques for detecting and correcting encoded data. In one embodiment, a system for detecting and correcting errors in a plurality of data bits comprises a static memory configured to store a plurality of data bits; a systematic encoder configured to convert the plurality of data bits into a codeword; a systematic parity check encoder configured to convert the codeword into a syndrome; and a syndrome decoder configured to evaluate the syndrome based on preset criteria used to determine whether the syndrome corresponds to an uncorrectable error. A binary [16, 8, 5] code is used to encode the plurality of data bits.

Abstract: A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: To perform error detection and correction on a data sector, syndromes are calculated and used to determine error values and error locations. Logarithmic calculations in Galois field need to be performed to determine the error locations using the syndromes. Finite field vectors are represented as “complex” numbers of the form Az+B. An algorithm is performed using the field vectors represented as complex numbers to generate the error locations. The algorithm requires the use of logarithm calculations. The results of the logarithmic calculations are looked up in two (or more) log tables. The log tables store all the possible results of the logarithm calculations. The log tables store significantly less bits than prior art techniques, reducing the amount of storage space required by a factor of 171. Techniques for controlling accesses to the log tables in an efficient manner are also provided.