Patents by Inventor Martin B. Mollat
Martin B. Mollat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8436635Abstract: A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.Type: GrantFiled: September 1, 2009Date of Patent: May 7, 2013Assignee: Texas Instruments IncorporatedInventors: Martin B. Mollat, Doug Weiser, Fan-Chi Hou
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Patent number: 8174077Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: GrantFiled: July 26, 2011Date of Patent: May 8, 2012Assignee: Texas Instruments IncorporatedInventors: Martin B. Mollat, Tony Thanh Phan
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Publication number: 20110278693Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Martin B. Mollat, Tony Thanh Phan
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Patent number: 7986010Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: GrantFiled: April 13, 2010Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Martin B. Mollat, Tony Thanh Phan
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Publication number: 20110050275Abstract: A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.Type: ApplicationFiled: September 1, 2009Publication date: March 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: MARTIN B. MOLLAT, DOUG WEISER, FAN-CHI FRANK HOU
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Patent number: 7838429Abstract: A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.Type: GrantFiled: July 18, 2007Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Tony Phan, Kyle M. Flessner, Martin B. Mollat, Connie Wang, Arthur Pan, Eric William Beach, Michelle R. Keramidas, Karen Elizabeth Burks
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Patent number: 7776625Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a substrate having a sub-surface feature and a surface feature, and determining a location of the sub-surface feature relative to the surface feature using a scatterometer.Type: GrantFiled: June 9, 2006Date of Patent: August 17, 2010Assignee: Texas Instruments IncorporatedInventors: Martin B. Mollat, Christopher C. Baum, Jonathan W. VanBuskirk
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Publication number: 20100193868Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Martin B. Mollat, Tony Thanh Phan
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Patent number: 7709329Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: GrantFiled: February 20, 2007Date of Patent: May 4, 2010Assignee: Texas Instruments IncorporatedInventors: Martin B. Mollat, Tony Thanh Phan
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Publication number: 20090023263Abstract: A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.Type: ApplicationFiled: July 18, 2007Publication date: January 22, 2009Applicant: Texas Instruments IncorporatedInventors: Tony Phan, Kyle M. Flessner, Martin B. Mollat, Connie Wang, Arthur Pan, Eric William Beach, Michelle R. Keramidas, Karen Elizabeth Burks
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Publication number: 20080197451Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Inventors: Martin B. Mollat, Tony Thanh Phan
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Patent number: 7415378Abstract: The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.Type: GrantFiled: January 31, 2005Date of Patent: August 19, 2008Assignee: Texas Instruments incorporatedInventors: Martin B. Mollat, Milind V. Khandekar, Tony T. Phan, Kyle M. Flessner
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Publication number: 20070287204Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a substrate having a sub-surface feature and a surface feature, and determining a location of the sub-surface feature relative to the surface feature using a scatterometer.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Applicant: Texas Instruments IncorporatedInventors: Martin B. Mollat, Christopher C. Baum, Jonathan W. VanBuskirk
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Patent number: 7262109Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).Type: GrantFiled: August 3, 2005Date of Patent: August 28, 2007Assignee: Texas Instruments IncorporatedInventors: John Lin, Tony T. Phan, Philip L. Hower, William C. Loftin, Martin B. Mollat
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Patent number: 7118958Abstract: The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer (185) over a substrate (110), and forming a refractory metal layer (210) having a thickness (t1) over the substrate (110), at least a portion of the refractory metal layer (210) extending over the material layer (185). The method further includes reducing the thickness (t2) of the portion of the refractory metal layer (210) extending over the material layer (185), thereby forming a thinned refractory metal layer (310), and reacting the thinned refractory metal layer (310) with at least a portion of the material layer (185) to form an electrode (440) for use in a capacitor.Type: GrantFiled: March 3, 2005Date of Patent: October 10, 2006Assignee: Texas Instruments IncorporatedInventors: Tony T. Phan, Martin B. Mollat