Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.

Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.

Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.

Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.

Abstract: A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.

Abstract: Circuit analysis and modification by receiving a first description of a circuit, the first description having a first level of detail, receiving a second description of the circuit, the second description having a second level of detail, performing a circuit simulation according to the first description, identifying an active node of the first description according to the simulation, and modifying the second description according to the active node.

Abstract: The present disclosure relates to storing data in a computer system. The computer system comprising a main memory coupled to a processor and a cache hierarchy. The main memory comprises a predefined bit pattern replacing existing data of the main memory. Aspects include storing the predefined bit pattern into a reference storage of the computer system. At least one bit in a cache directory entry of a first cache line of the cache hierarchy can be set. Upon receiving a request to read the content of the first cache line, the request can be redirected to the predefined bit pattern in the reference storage based on the value of the set bit of the first cache line.

Abstract: Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.

Abstract: A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.

Abstract: The present disclosure relates to storing data in a computer system. The computer system comprising a main memory coupled to a processor and a cache hierarchy. The main memory comprises a predefined bit pattern replacing existing data of the main memory. Aspects include storing the predefined bit pattern into a reference storage of the computer system. At least one bit in a cache directory entry of a first cache line of the cache hierarchy can be set. Upon receiving a request to read the content of the first cache line, the request can be redirected to the predefined bit pattern in the reference storage based on the value of the set bit of the first cache line.

Abstract: Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.

Abstract: Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.