Abstract: A damper actuator for a ventilation damper serves as both a control device for the ventilation damper and a fire and smoke rated device for the ventilation damper. The damper actuator includes a modulating motor controller, a two-point motor controller, and a thermal switch or switch like device that is operative to switch control of the motor from the modulating motor controller used during normal operation, to the two-point motor controller during a fire and smoke condition. The damper actuator provides an automatic and permanent disabling (by-passing) of the modulating motor controller functions the first time a pre-determined temperature level (switch point) is reached via the thermal switch or switch like device. Once the modulating motor controller is disabled, the actuator no longer supports the advanced motor control functions (i.e. the modulating control).

Abstract: A vehicle management system includes a vehicle location system providing location information indicative of a location of a vehicle. A integrated transportation management tool is coupled to the vehicle location system and receives the location information. The integrated transportation management tool initiates a course of action in response to the location information. The course of action may include altering at least one of speed, capacity and route of the vehicle. Passenger information may also be used by the integrated transportation management tool to determine the course of action. Multiple integrated transportation management tools may be coupled by a network to provide distributed management of vehicles.

Abstract: A configuration for testing a plurality of memory chips on a wafer, in which needles are used to supply the memory chips with supply voltages, an initialization signal, a read signal, a clock signal as well as address, data and control signals. The address, data and control signals are in this case produced by a logic device disposed in an edge area of the memory chip and are supplied directly to the memory chips.

Abstract: A method and a circuit configuration deactivate an input of a receiving circuit when a first edge occurs, during processing of a digital input signal. When a falling edge occurs, the input is only reactivated after a delay. An influence of signal interference and incorrect interpretations of the signal can thereby be reduced. The method and circuit configuration are employed in particular with clock signals in which only one edge is used for signal evaluation.

Abstract: An integrated semiconductor circuit has at least two supply networks that are supplied independently of one another. The two supply networks include a first, load supply network, which is associated with a load circuit, and a second, driver supply network, which is associated with a driver circuit. Each supply network has a ground path with ground lines and a supply path with supply potential lines which are separate from the ground path. A compensating circuit is provided which alternatively couples the ground paths and/or the supply paths of the at least two supply networks to one another.

Abstract: The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to output data to a data output. In addition, the integrated circuit has a control unit generating the internal clock signal from the external clock signal. The control unit has a phase shift unit that, in the normal mode of operation, effects a phase shift of the internal clock signal generated by the control unit with respect to the external clock signal. In addition, the integrated circuit has a detector unit determining the capacitive load on the data output. The detector unit supplying the phase shift unit with a corresponding detector signal on the basis of which the phase shift is set.

Abstract: On the leads of an integrated semiconductor chip which establish a connection to external terminals of a supply voltage, highly clocked current pulses may result in the excitation of potential fluctuations through to resonance oscillations at an internal terminal of the respective lead. In order to attenuate these potential fluctuations, a resistance is prescribed for one or more leads, which resistance is large enough to attenuate the potential fluctuations but is small enough to cause only a predetermined maximum permissible voltage drop on the respective lead. The respective resistance can be obtained by using a material having a corresponding resistivity or by reducing the conductor cross section with a notch along the lead.

Abstract: A configuration is provided for testing chips produced from a wafer. The chips are supplied with test signals through the use of a test head. The test signals can be applied in a serial or parallel manner to the chips which are actually in the wafer, through the use of test lines provided in a sawing edge of the chips.

Abstract: The circuit has a first input for supplying a first signal (S1) to a series circuit made from a plurality of basic elements. Each basic element has a memory (M) for storing the signal level which is applied to the input of the basic element, and the output of a storage element (M) is connected to the input of a next basic element. Furthermore, the circuit has a second input for supplying a second signal (S2) which is connected to a control input of each basic element. Given a first level of the second signal, the storage elements (M) take up the signal level stored in the preceding storage element, and given a second level of the second signal, the storage elements (M) retain the signal level respectively stored in them. Furthermore, the circuit has comparator units (XOR) to which, in each case, the signal levels stored by the storage units (M) of two adjacent basic elements are supplied.

Abstract: The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to output data to a data output. In addition, the integrated circuit has a control unit generating the internal clock signal from the external clock signal. The control unit has a phase shift unit that, in the normal mode of operation, effects a phase shift of the internal clock signal generated by the control unit with respect to the external clock signal. In addition, the integrated circuit has a detector unit determining the capacitive load on the data output. The detector unit supplying the phase shift unit with a corresponding detector signal on the basis of which the phase shift is set.

Abstract: A dynamic semiconductor memory device of the random access type having an initialization circuit which controls the switch-on operation of the semiconductor memory device and of its circuit components. The initialization circuit supplies a supply voltage stable signal once the supply voltage has been stabilized after the switching-on of the semiconductor memory device. The initialization circuit has an advance detector circuit, which detects a predetermined level state of an externally applied clock control signal chronologically before the supply voltage stable signal is generated and, as a reaction to this, supplies a first enable signal for unlatching the control circuit provided for the proper operation of the semiconductor memory device.

Abstract: An input circuit has an inverter and a differential amplifier, which are respectively connected on an input side to an input and on an output side to an output of the input circuit. The input circuit has two operating modes defined by an activation signal, the differential amplifier being activated and the inverter being deactivated in a first operating mode, and the differential amplifier being deactivated and the inverter being activated in a second operating mode. In this manner, the input circuit has the advantage of selective operation with LVTTL or SSTL levels.

Abstract: An output driver for an integrated semiconductor chip overcomes voltage fluctuations at connections of a supply voltage of the semiconductor chip generated by a rapid-switching output driver. The output driver includes a switching circuit which is connected to the supply voltage and contains two switching transistors, as well as a regulating circuit for voltage-dependent regulation of switching characteristics of the switching circuit. As a result of the regulating circuit, the switching characteristics of at least one transistor of the switching circuit are regulated in such a way as to counteract voltage fluctuations arising at the connections to the supply voltage through the switching process of the switching circuit.