Patents by Inventor Martin Domeij
Martin Domeij has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378273Abstract: A power semiconductor device includes a substrate having a body region and a drift layer; a trench formed in the substrate; a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and a conductive material provided within the trench over the gate dielectric structure.Type: ApplicationFiled: May 26, 2023Publication date: November 23, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kwangwon LEE, Youngho SEO, Martin DOMEIJ, Kyeongseok PARK
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Patent number: 11817478Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.Type: GrantFiled: December 23, 2020Date of Patent: November 14, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume Roig-Guitart, Fredrik Allerstam, Thomas Neyer, Andrei Konstantinov, Martin Domeij, Jangkwon Lim
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Publication number: 20230282693Abstract: Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include a trench channel adjacent to the trench and two doped pillars of a second conductivity type extending on each side of the first conductivity type doped pillar where a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material may be at least 1.6 to 1.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kwangwon LEE, Youngho SEO, Hrishikesh DAS, Martin DOMEIJ, Kyeongseok PARK
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Publication number: 20220199764Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume ROIG-GUITART, Fredrik ALLERSTAM, Thomas NEYER, Andrei KONSTANTINOV, Martin DOMEIJ, Jangkwon LIM
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Publication number: 20210050420Abstract: A power semiconductor device includes a substrate having a body region and a drift layer; a trench formed in the substrate; a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and a conductive material provided within the trench over the gate dielectric structure.Type: ApplicationFiled: October 29, 2019Publication date: February 18, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kwangwon LEE, Youngho SEO, Martin DOMEIJ, Kyeongseok PARK
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Patent number: 10749002Abstract: A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on RDS-ON.Type: GrantFiled: November 12, 2019Date of Patent: August 18, 2020Assignee: Semiconductor Components Industries, LLCInventor: Martin Domeij
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Publication number: 20200083331Abstract: A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on RDS-ON.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Martin DOMEIJ
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Patent number: 10504995Abstract: A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on RDS-ON.Type: GrantFiled: August 9, 2018Date of Patent: December 10, 2019Assignee: Semiconductor Components Industries, LLCInventor: Martin Domeij
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Patent number: 10453950Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.Type: GrantFiled: June 19, 2017Date of Patent: October 22, 2019Inventor: Martin Domeij
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Publication number: 20170288048Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.Type: ApplicationFiled: June 19, 2017Publication date: October 5, 2017Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventor: Martin DOMEIJ
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Patent number: 9685550Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region has a first portion disposed between the first doped region and the body region, and the second doped region has a second portion disposed between the first doped region and the gate dielectric.Type: GrantFiled: December 28, 2015Date of Patent: June 20, 2017Assignee: Fairchild Semiconductor CorporationInventor: Martin Domeij
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Patent number: 9590047Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.Type: GrantFiled: April 4, 2012Date of Patent: March 7, 2017Assignee: FAIRCHILD SEMICONDUCTOR CORPORATIONInventor: Martin Domeij
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Patent number: 9478629Abstract: In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region.Type: GrantFiled: January 11, 2013Date of Patent: October 25, 2016Assignee: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Martin Domeij, Benedetto Buono
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Publication number: 20160190300Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region has a first portion disposed between the first doped region and the body region, and the second doped region has a second portion disposed between the first doped region and the gate dielectric.Type: ApplicationFiled: December 28, 2015Publication date: June 30, 2016Inventor: Martin DOMEIJ
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Publication number: 20150115283Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.Type: ApplicationFiled: April 4, 2012Publication date: April 30, 2015Applicant: Fairchild Semiconductor CorporationInventor: Martin Domeij
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Patent number: 8907351Abstract: In one general aspect, a silicon carbide (SiC) bipolar junction transistor (BJT) can include a collector region, a base region having an extrinsic part, and an emitter region. The SiC BJT can include a surface passivation layer deposited on the extrinsic part between an emitter contact contacting the emitter region and a base contact contacting the base region. The SiC BJT can also include a surface gate at the surface passivation layer where the surface gate has at least a portion disposed over the extrinsic part of the base region.Type: GrantFiled: October 31, 2013Date of Patent: December 9, 2014Assignee: Fairchild Semiconductor CorporationInventor: Martin Domeij
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Patent number: 8853827Abstract: In at least one aspect, an apparatus can include a silicon carbide material, a base contact disposed on a first portion of the silicon carbide material, and an emitter contact disposed on a second portion of the silicon carbide material. The apparatus can also include a dielectric layer disposed on the silicon carbide material and disposed between the base contact and the emitter contact, and a surface electrode disposed on the dielectric layer and separate from the base contact and the emitter contact.Type: GrantFiled: January 11, 2013Date of Patent: October 7, 2014Assignee: Fairchild Semiconductor CorporationInventor: Martin Domeij
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Patent number: 8829533Abstract: The present invention relates to a semiconductor device (1) in silicon carbide, with a highly doped substrate region (11) and a drift region (12). The present invention specifically teaches that an additional layer (13) is positioned between the highly doped substrate region (11) and the drift region (12), the additional layer (13) thus providing a wide safe operating area at subsequently high voltages and current densities.Type: GrantFiled: April 10, 2008Date of Patent: September 9, 2014Assignee: Fairchild Semiconductor CorporationInventor: Martin Domeij
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Publication number: 20140054612Abstract: A silicon carbide (SiC) bipolar junction transistor (BJT) including a collector region and a base region having an extrinsic part. The SiC BJT including an emitter region and a surface passivation layer deposited on the extrinsic part between an emitter contact contacting the emitter region and a base contact contacting the base region. The SiC BJT also including a surface gate at the surface passivation layer.Type: ApplicationFiled: October 31, 2013Publication date: February 27, 2014Applicant: Fairchild Semiconductor CorporationInventor: Martin DOMEIJ
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Patent number: 8378390Abstract: The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts (1, 2) on the transistor is given a negative electric surface potential with respect to the potential in the bulk SiC. The present disclosure also relates to a method for increasing the current gain in a silicon carbide (SiC) bipolar junction transistor (BJT) by the reduction of the surface recombination at the SiC surface between the emitter and base contacts (1, 2) of the transistor.Type: GrantFiled: September 23, 2011Date of Patent: February 19, 2013Assignee: Fairchild Semiconductor CorporationInventor: Martin Domeij