Patents by Inventor Martin G. Walker

Martin G. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for extraction of parasitic interconnect impedance including inductance
    Patent number: 6643831
    Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: November 4, 2003
    Assignee: Sequence Design, Inc.
    Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker
  • Method and system for extraction of parasitic interconnect impedance including inductance
    Publication number: 20020104063
    Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.
    Type: Application
    Filed: January 24, 2002
    Publication date: August 1, 2002
    Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker
  • Method and system for extraction of parasitic interconnect impedance including inductance
    Patent number: 6381730
    Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: April 30, 2002
    Assignee: Sequence Design, Inc.
    Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker