Patents by Inventor Martin Gruber

Martin Gruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187326
    Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 15, 2023
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Publication number: 20230178428
    Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Thorsten Meyer, Fee Hoon Wendy Wong, Thomas Behrens, Eric Lopez Bonifacio, Chau Fatt Chiang, Irmgard Escher-Poeppel, Giovanni Ragasa Garbin, Martin Gruber, Tien Shyang Law, Mohamad Azian Mohamed Azizi, Si Hao Vincent Yeo
  • Patent number: 11600558
    Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 7, 2023
    Assignee: Infineon Technologies AG
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Publication number: 20230051100
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 16, 2023
    Inventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan
  • Publication number: 20220384305
    Abstract: A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 1, 2022
    Inventors: Edward Fuergut, Anton Mauder, Stephan Voss, Martin Gruber
  • Patent number: 11515244
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 29, 2022
    Assignee: Infineon Technologies AG
    Inventors: Bun Kian Tay, Mei Yih Goh, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Thorsten Scharf, Chee Voon Tan
  • Publication number: 20220375830
    Abstract: A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 24, 2022
    Inventors: Edward Fuergut, Martin Gruber, Herbert Hopfgartner, Bernd Schmoelzer
  • Publication number: 20220375832
    Abstract: A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 24, 2022
    Inventors: Edward Fuergut, Martin Gruber, Herbert Hopfgartner, Bernd Schmoelzer
  • Patent number: 11502042
    Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Martin Gruber, Thorsten Scharf, Peter Strobel
  • Publication number: 20220285283
    Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Edward Fuergut, Ravi Keshav Joshi, Ralf Siemieniec, Thomas Basler, Martin Gruber, Jochen Hilsenbeck, Dethard Peters, Roland Rupp, Wolfgang Scholz
  • Patent number: 11367683
    Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 21, 2022
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Ravi Keshav Joshi, Ralf Siemieniec, Thomas Basler, Martin Gruber, Jochen Hilsenbeck, Dethard Peters, Roland Rupp, Wolfgang Scholz
  • Publication number: 20220165687
    Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.
    Type: Application
    Filed: October 15, 2021
    Publication date: May 26, 2022
    Applicant: Infineon Technologies AG
    Inventors: Thorsten MEYER, Thomas BEMMERL, Martin GRUBER, Martin Richard NIESSNER
  • Patent number: 11338237
    Abstract: A hollow filter element for insertion into an openable filter housing has a filter medium body configured as a hollow body surrounding an inwardly positioned flow space. At least one end disk is connected to the filter medium body and covers an axial end face of the filter medium body. A positioning element is arranged at the at least one end disk and interacts with a housing-associated blade of the filter housing. The positioning element receives the housing-associated blade with form fit in two different transverse directions relative to the longitudinal axis of the filter medium body. The positioning element has a positioning recess.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 24, 2022
    Assignee: MANN+HUMMEL GmbH
    Inventors: Christoph Wittmers, Nadine Donauer, Andreas Franz, Marcel Holzwarth, Pedro Miguel Pereira Madeira, Joachim-Paul Krieger, Martin Gruber, Manfred Winter, Torsten Fritzsching
  • Publication number: 20220157774
    Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.
    Type: Application
    Filed: October 15, 2021
    Publication date: May 19, 2022
    Applicant: Infineon Technologies AG
    Inventors: Thorsten MEYER, Martin GRUBER, Thorsten SCHARF
  • Patent number: 11325676
    Abstract: In an electric drive device for a bicycle, there is an electric motor with an output shaft and an angular gear by which the output shaft is connectable to a wheel of the bicycle in a drive-effective manner, and a fastening device is provided, carrying the electric motor and configured to fasten the electric motor to a rotation axle of the wheel.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 10, 2022
    Assignee: ALPINE DRIVE GMBH
    Inventors: Martin Gruber, Reinhold Gruber
  • Publication number: 20220112586
    Abstract: The invention relates to a cold rolled steel sheet having a composition consisting of (in wt. %): C 0.15-0.25; Si 0.5-1.6; Mn 2.2-2.8; Cr?0.8; Mo?0.2; Al 0.03-1.0; Nb?0.04; V?0.04; Ti 0.02-0.04; B 0.001-0.005; balance Fe apart from impurities, wherein the impurity contents of Cu and Ni are limited to ?0.15, the cold rolled steel has a multiphase microstructure comprising a matrix of bainitic ferrite and ?10 vol. % polygonal ferrite and the tensile strength (Rm) is 980-1500 MPa.
    Type: Application
    Filed: November 28, 2019
    Publication date: April 14, 2022
    Inventors: Florian WINKELHOFER, Thomas HEBESBERGER, Martin GRUBER, Johannes REHRL
  • Publication number: 20220112575
    Abstract: A cold rolled steel strip or sheet has a composition consisting of (in wt. %): C 0.15-0.25; Si 0.5-1.6; Mn 2.2-3.2; Cr?0.8; Mo?0.2; Al 0.03-1.0; Nb?0.04; V?0.04; Ti 0.01-0.04; B 0.001-0.010; TUB 5-30; Cu?0.15; Ni?0.15; Ca?0.01; balance Fe apart from impurities, where the cold rolled steel has a multiphase microstructure comprising a matrix mainly composed of tempered martensite and has a tensile strength (Rm) of at least 1380 MPa.
    Type: Application
    Filed: November 28, 2019
    Publication date: April 14, 2022
    Inventors: Johannes REHRL, Martin GRUBER, Florian WINKELHOFER, Thomas HEBESBERGER
  • Publication number: 20220102301
    Abstract: A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 31, 2022
    Inventors: Clemens Roessler, Silke Auchter, Martin Gruber, Johanna Elisabeth Roessler
  • Publication number: 20220102311
    Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 31, 2022
    Inventors: Edward Fuergut, Martin Gruber, Petteri Palm, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Patent number: 11264356
    Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf